saa7803 NXP Semiconductors, saa7803 Datasheet - Page 27

• Manufacturer Part Number: saa7803
• Description: Saa7803 One Chip Cd Audio Device
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 13695
Objective data sheet
The first and last tap can be programmed via register PLLEqualiser.
Usable EFM bit clock range:
following constraints:
Only in this range a reliable bit detection is possible. If input channel bit rate is above
2
Remark: While these are theoretical limits, a real-life application should keep a safety
margin. When the bit clock is relatively low, the internal filter will filter off more noise,
yielding a better performance. If the theoretical upper limit is approached, playability (e.g.
black dot performance) will drop significantly. The decoder will only be able to correct the
biggest correctable burst error of 16 frames if f
Taken this restriction on the decoder into account, the range is:
Digital HF PLL:
the PLL itself is very limited. To overcome this difficulty, two capture aids are present.
When using automatic locking, the PLL will switch state based on the difference between
expected distance and actual distance between syncs.
In total, three different PLL operation modes exist:
First, PLL operation during in-lock is explained. This is the normal on-track situation. After
this, the lock-detection and the two capture aids are explained.
PLL in-lock characteristics:
the frequency domain. PLL operation is completely linear during in-lock situations. The
open-loop response of the PLL (Bode diagram) is given in
Fig 17. Equalizer
It should be less than 2
It should be larger than 0.25
Or: 0.25 < f
0.25 < f
In-lock (normal operation); the PLL frequency matches the frequency of the channel bits
with an accuracy error less than 1 %
Inner lock aid (capture aid 1); the PLL frequency matches the frequency of the channel
bits with an accuracy error between 1 % and 10 %
Outer lock aid (capture aid 2); the PLL frequency deviates more than 10 % from the
channel bit frequency.
f
sys
then the PLL will saturate to two times the system clock frequency f
bit
/f
sys
sys
< 1.7.
< 2.
The digital PLL will recover the channel bit clock. The capture range of
Rev. 01 — 19 April 2005
in
f
sys
1
The PLL behavior during in-lock can best be explained in
The channel bit clock frequency should always obey the
D
f
sys
D
out
D
bit
/f
sys
D
< 1.7.
001aab761
D
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Figure
One chip CD audio device
1
18.
SAA7803
sys
.
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