saa7803 NXP Semiconductors, saa7803 Datasheet - Page 47

• Manufacturer Part Number: saa7803
• Description: Saa7803 One Chip Cd Audio Device
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 13695
Objective data sheet
The command byte is the first to be loaded and can be considered as two nibbles. The
upper (most significant) nibble represents the command itself whilst the lower (least
significant) nibble tells the PDSIC how many parameter bytes to expect. The command
byte gets placed into memory location 31h (called oldcom).
Subsequently, parameter bytes get loaded sequentially and these get placed into a stack
space that has been reserved within the memory (locations 30h to 2Bh). With each
parameter byte that is loaded, the value in oldcom is decremented. In other words, the
byte count decreases until it reaches 0, then the PDSIC knows it has a complete servo
command with a command byte and its full complement of parameter bytes. At this point,
the PDSIC acts upon the command and the appropriate function is carried out based
upon the values in the stack space.
There are two special case servo commands: Write_parameter (opcode = A2h) and
Write_decoder_reg (opcode = D1h).
Write_parameter allows the microprocessor to write directly to any memory location. It
carries two parameter bytes; the memory address and the data that is to be written. When
this command is executed the command byte is loaded into oldcom and the first
parameter byte (<RAM_address>) is loaded onto the stack. The second parameter byte
(<data>) is loaded directly into the location specified by <RAM_address>.
Write_decoder_reg allows decoder registers to be written to when the I
being used. This command carries only one parameter byte, which is the decoder
register / data pair (2 nibbles). When this command is received by the PDSIC, the
register / data pair is loaded into memory location 4Dh.
The servo read commands operate slightly differently in that they carry no parameter
bytes and the lower nibble of the command byte is always 0 to indicate this. When the
PDSIC receives a read command it will make certain information available (mostly from
memory, although some status information is retrieved from the decoder) on the serial
interface for collection by the microprocessor.
If a sequence of values are being read from the servo RAM (e.g. a series of values related
to a PID loop), it is important to ensure that the values are consistent with each other, i.e.
to ensure the servo has not updated some of the values during the period they are read.
Therefore, an interrupt signal is available from the servo to the ARM which raises an IRQ
when it is safe to read related values. This can also be monitored by the state of the servo
register bits SRV_FC0 and SRV_FC1 shown in
these signals and raises an IRQ whenever the correct state is achieved. Applying a pulse
to the ‘inreq_clr’ register bit will then clear the interrupt. If the interrupt is not cleared, it will
automatically be reset when the valid reading state is no longer true.
Figure 28
interrupt that does not get cleared by the ARM. Int #2 and Int #3 are shown being cleared
by pulses being written to the inreq_clr register. The time between interrupts is
approximately 15 s and the total interrupt cycle time is approximately 60 s.
shows the operation of the IRQ signal. Int #1 shows the full duration of an
Rev. 01 — 19 April 2005
Table
13. The interrupt generator monitors
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
One chip CD audio device
SAA7803
2
C-bus interface is
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