saa7803 NXP Semiconductors, saa7803 Datasheet - Page 45

• Manufacturer Part Number: saa7803
• Description: Saa7803 One Chip Cd Audio Device
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 13695
Objective data sheet
6.6.8.2 Position error
6.6.8.3 Motor control loop gains (K
6.6.8.4 Operation modes
The set point can be programmed via register MotorFreqSet. The selection of the motor
frequency input is programmed via MotorGainSet2(MotorFreqSource).
The position error will be used to fine tune the motor speed during ‘slave mode’, where the
incoming EFM bit rate is locked on the programmed fixed I
set point must be chosen between 118 and 128, since this is the usable FIFO size in the
decoder. See
information.
The set point can be programmed via register MotorFifoSet.
The control loop gains are all programmable through registers MotorGainSet1 and
MotorGainSet2. To be able to set integrator bandwidth low enough at high system clock
speeds an extra divider for the factors K
through the register MotorMultiplier.
The resulting K
multiplied by K
K
Please note the following:
The motor controller mode is programmed via register MotorControl. It can operate in
open loop by just sending a fixed power to the motor for start-up and stopping, closed
loop, or shut down. It also selects between PDM and PWM format.
Motor start and stop modes will put a fixed duty cycle PWM or fixed density PDM signal on
the motor outputs. During start or stop, motor speed can be monitored by reading
MotorIntLSB and MotorIntMSB.
MotorOv:
inside the PDM/PWM modulator block, or in the programmable gain stage. This is
signalled by the MotorOv interrupt, which can be read back on InterruptStatus2. The
interrupt disappears when the overflow disappears.
MotorOv can also automatically open SW1 and SW2 . This is enabled by writing a ’1’ to bit
OVFSW in register MotorControl.
I
•
•
_Mult.
K
input is passed through the integrator circuit, for a K
sample is passed through, for a K
through, and so on
For a DC input signal, K
the input varies quickly, the K
always give the same result, especially for low values of K
in the extreme becomes 1 out of every 128 samples. (The input samples to the block
that performs the K
clock periods.). Sub-sampling might affect the actual resulting gain.
F
_Mult operates by sampling the input; e.g. for K
When not setting the appropriate gains in the loop, an overflow might occur
Section “Data latency and FIFO operation” on page 35
F
I(tot)
_Mult. The integrator bandwidth must be scaled with the same factor
is then the K
F
Rev. 01 — 19 April 2005
_Mult multiplication occur at a rate of 1 sample every 24 system
F
P
, K
K
I
multiplied by K
F
F
F
_Mult should always give the same result. If however,
and K
K
F
F
_Mult of 0.25, every fourth sample is passed
_Mult combinations with the same product will not
I
and K
I
)
F
I
_Mult. The resulting K
is added. These factors can be written
F
_Mult = 1, every sample of the
F
_Mult of 0.5, every second
2
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
S-bus bclk output speed. The
F
One chip CD audio device
_Mult, where the sampling
for more
SAA7803
F(tot)
is then the K
45 of 74
F