lf3320 LOGIC Devices Incorporated, lf3320 Datasheet - Page 10

• Manufacturer Part Number: lf3320
• Description: Horizontal Digital Image Filter
• Manufacturer: LOGIC Devices Incorporated

DEVICES INCORPORATED
tional considerations, refer to the cor-
responding mode of operation section.
FUNCTIONAL DESCRIPTION
ALUs
The ALUs double the number of filter
taps available, when symmetric coeffi-
cient sets are used, by pre-adding data
values which are then multiplied by
a common coefficient (see Figure 12).
The ALUs can perform two opera-
tions: A+B and B–A. Bit 0 of Configu-
ration Register 0 determines the oper-
ation of the ALUs in Filter A.
Bit 0 of Configuration Register 2 deter-
mines the operation of the ALUs
in Filter B. A+B is used with
F
F
IGURE
IGURE
Even-Tap, Even-Symmetric
8
12. S
13. I/D R
EVEN-TAP MODE
A
7
ALU
Coefficient Set
6
B
even-symmetric coef-
5
YMMETRIC
A
4
ALU
EGISTER
3
B
2
C
COEF 7
COEF 6
1
OEFFICIENT
D
ATA
P
ATHS
ficient sets. B–A is used with odd-
symmetric coefficient sets.
Also, either the A or B operand may
be set to 0. Bits 1 and 2 of Configura-
tion Register 0 and Configuration Reg-
ister 2 control the ALU inputs in Fil-
ters A and B respectively. A+0 or B+0
are used with asymmetric coefficient
sets.
Interleave/Decimation Registers
The Interleave/Decimation Registers
(I/D Registers) feed the ALU inputs.
They allow the device to filter up to
sixteen data sets interleaved into the
same data stream without having to
separate the data sets. The I/D Regis-
ters should be set to a length equal
to the number of data sets interleaved
S
ET
Odd-Tap, Even-Symmetric
E
7
XAMPLES
A
ODD-TAP MODE
Coefficient Set
6
ALU
5
B
2-10
4
A
3
ALU
2
B
1
Delay Stage N 1
Delay Stage N
COEF 7
COEF 6
2
Horizontal Digital Image Filter
together.
For example, if two data sets are
interleaved together, the I/D Registers
should be set to a length of two. Bits
1 through 4 of Configuration Register
1 and Configuration Register 3 deter-
mine the length of the I/D Registers in
Filters A and B respectively.
The I/D Registers also facilitate using
decimation to increase the number of
filter taps. Decimation by N is accom-
plished by reading the filter’s output
once every N clock cycles. The device
supports decimation up to 16:1. With
no decimation, the maximum number
of filter taps is sixteen. When decimat-
ing by N, the number of filter taps
becomes 16N because there are N–1
clock cycles when the filter’s output is
Video Imaging Products
ODD-TAP INTERLEAVE MODE
Even-Tap, Odd-Symmetric
8
A
7
ALU
Coefficient Set
6
B
5
A
4
ALU
3
6/22/2007–LDS.3320-R
B
2
LF3320
COEF 7
COEF 6
1
2