lf3320 LOGIC Devices Incorporated, lf3320 Datasheet - Page 4

• Manufacturer Part Number: lf3320
• Description: Horizontal Digital Image Filter
• Manufacturer: LOGIC Devices Incorporated

DEVICES INCORPORATED
registered output port for the lower
twelve bits of the 16-bit Filter B
output.
ROUT
In Single Filter Mode, ROUT
a 12-bit registered cascade output
port. ROUT
be connected to RIN
LF3320. In Dual Filter Mode, ROUT
is a 4-bit registered output port for
the upper four bits of the 16-bit Filter
B output. In this mode, ROUT
disabled.
Controls
LDA — Coefficient A Load
When LDA is LOW, data on CFA
is latched into the Filter A LF Inter-
face
When LDA is HIGH, data is not
loaded into the Filter A LF Interface
When enabling the LF Interface
data input, a HIGH to LOW transition
of LDA is required in order for the
input circuitry to function properly.
Therefore, LDA must be set HIGH
immediately after power up to ensure
proper operation of the input circuitry
(see the LF Interface
full discussion).
CENA — Coefficient Address Enable A
When CENA is LOW, data on CAA
is latched into Coefficient Address
Register A on the rising edge of
CLK. When CENA is HIGH, data on
CAA
ter’s contents will not be changed.
LDB — Coefficient B Load
When LDB is LOW, data on CFB
latched into the Filter B LF Interface
on the rising edge of CLK. When LDB
is HIGH, data is not loaded into the
Filter B LF Interface
the LF Interface
HIGH to LOW transition of LDB is
required in order for the input cir-
cuitry to function properly. Therefore,
TM
7-0
11-0
on the rising edge of CLK.
is not latched and the regis-
— Reverse Cascade Output
11-0
TM
on one device should
for data input, a
TM
TM
11-0
. When enabling
section for a
of another
11-0
11-4
TM
is
11-0
11-0
for
is
7-0
TM
TM
3-0
is
.
LDB must be set HIGH immediately
after power up to ensure proper oper-
ation of the input circuitry (see the
LF Interface
sion).
CENB — Coefficient Address Enable B
When CENB is LOW, data on CAB
is latched into Coefficient Address
Register B on the rising edge of CLK.
When CENB is HIGH, data on CAB
is not latched and the register’s con-
tents will not be changed.
TXFRA — Filter A LIFO Transfer
TXFRA is used to change which LIFO
in the data reversal circuitry sends
data to the reverse data path and
which LIFO receives data from the
forward data path in Filter A. When
TXFRA goes LOW, the LIFO sending
data to the reverse data path becomes
the LIFO receiving data from the for-
ward data path, and the LIFO receiv-
ing data from the forward data path
becomes the LIFO sending data to
the reverse data path. The device
must see a HIGH to LOW transition
of TXFRA in order to switch LIFOs.
TXFRA is latched on the rising edge
of CLK.
TXFRB — Filter B LIFO Transfer
TXFRB is used to change which LIFO
in the data reversal circuitry sends
data to the reverse data path and
which LIFO receives data from the
forward data path in Filter B. When
TXFRB goes LOW, the LIFO sending
data to the reverse data path becomes
the LIFO receiving data from the for-
ward data path, and the LIFO receiv-
ing data from the forward data path
becomes the LIFO sending data to
the reverse data path. The device
must see a HIGH to LOW transition
of TXFRB in order to switch LIFOs.
TXFRB is latched on the rising edge of
CLK.
Control
Control
TM
section for a full discus-
2-4
Horizontal Digital Image Filter
7-0
7-0
ACCA — Accumulator A Control
When ACCA is HIGH, Accumulator
A is enabled for accumulation and the
Accumulator A Output Register is dis-
abled for loading. When ACCA is
LOW, no accumulation is performed
and the Accumulator A Output Regis-
ter is enabled for loading. ACCA is
latched on the rising edge of CLK.
ACCB — Accumulator B Control
When ACCB is HIGH, Accumulator B
is enabled for accumulation and the
Accumulator B Output Register is dis-
abled for loading. When ACCB is
LOW, no accumulation is performed
and the Accumulator B Output Regis-
ter is enabled for loading. ACCB is
latched on the rising edge of CLK.
SHENA — Filter A Shift Enable
In Dual Filter Mode, SHENA enables
or disables the loading of data into the
Input (DIN
isters. When SHENA is LOW, data
is latched into the Input/Cascade Reg-
isters and shifted through the I/D
Registers on the rising edge of CLK.
When SHENA is HIGH, data can
not be loaded into the Input/Cascade
Registers or shifted through the I/D
Registers and their contents will not
be changed.
In Single Filter Mode, SHENA also
enables or disables the loading of
data into the Reverse Cascade Input
(RIN
(COUT
(ROUT
It is important to note that in Single
Filter Mode, both SHENA and SHENB
should be connected together. Both
must be active to enable data loading
in Single Filter Mode. SHENA is
latched on the rising edge of CLK.
SHENB — Filter B Shift Enable
In Dual Filter Mode, SHENB enables
or disables the loading of data into
the Reverse Cascade Input (RIN
Video Imaging Products
11-0
11-0
11-0
), Cascade Output
), Reverse Cascade Output
) and Filter B I/D Registers.
11-0
) and Filter A I/D Reg-
6/22/2007–LDS.3320-R
LF3320
11-0
),