lf3320 LOGIC Devices Incorporated, lf3320 Datasheet - Page 6

• Manufacturer Part Number: lf3320
• Description: Horizontal Digital Image Filter
• Manufacturer: LOGIC Devices Incorporated

DEVICES INCORPORATED
LF Interface
halted until PAUSEB is returned to
a LOW state. This effectively allows
the user to load coefficients and con-
trol registers at a slower rate than the
master clock (see the LF Interface
section for a full discussion).
OPERATIONAL MODES
Single Filter Mode
In this mode, the device operates as a
single FIR filter (see Figure 4). It can
be configured to have as many as 32
taps if symmetric coefficient sets are
used. If asymmetric coefficient sets
are used, the device can be configured
to have as many as 16 taps. Cascade
ports are provided to facilitate cascad-
ing multiple devices to increase the
number of filter taps. Bit 1 in Configu-
ration Register 5 determines the filter
mode. In Single Filter Mode, DIN
is the data input for the filter and
DOUT
filter.
Dual Filter Mode
F
IGURE
N
15-0
TXFRA
TXFRB
COEF (N-1)
COEF 2
COEF 1
COEF 0
6. M
is the data output for the
DIN
RIN
TM
11-0
11-0
loading sequence is
ATRIX
12
Dual Filter Mode, N=8
Single FIlter Mode, N=16
12
12
12
12
-
VECTOR
A
ALU
0
B
M
TM
11-0
ULTIPLY
In this mode, the device operates as
two separate FIR filters (see Figure 5).
Each filter can be configured to have
as many as 16 taps if symmetric coef-
ficient sets are used. If asymmetric
coefficient sets are used, each filter can
be configured to have as many as 8
taps. In Dual Filter Mode, DIN11-0 is
the data input for Filter A. Either
RIN11-0 or DIN11-0 can be the data
input for Filter B. The Filter B input
is determined by Bit 2 in Configu-
ration Register 5. DOUT15-0 is the
data output for Filter A. COUT11-0
and ROUT3-0 together form the data
output for Filter B. COUT11-0 is
the twelve least significant bits and
ROUT3-0 is the four most significant
bits of the 16-bit Filter B output.
Matrix-vector Multiply Mode
In this mode, the LF3320 can be con-
figured to multiply a square matrix of
maximum size N (N = 8 or 16), multi-
plied by a matrix-vector of maximum
size [8,1] or [16,1]. The mathematical
representation for this operation is in
Figure 7. When configured in the dual
M
N
A
ODE
ALU
B
0
32
A
ALU
0
B
2-6
A
ALU
B
0
Horizontal Digital Image Filter
filter mode, the LF3320 can process
two matrix-vector multipliers simul-
taneously (i.e. [8x8][8x1]). In the
single filter mode, the LF3320 can
process a single matrix-vector multi-
ply (i.e. [16x16][16x1]). This mode of
operation allows the user to organize
data values (e.g. pixels) into an array
(e.g. blocks). This function is useful
for any application requiring the oper-
ation of matrix multiplication; a func-
tion that is used when generating
Discrete Cosine Transform coefficients
(DCT) for the purpose of further pro-
cessing.
When configuring the LF3320 for an
[8x8][8x1] matrix-vector operation, the
coefficient banks will require 8 coef-
ficient sets to be loaded into the coef-
ficient memory banks; each coefficient
set will have 8, 12-bit coefficients. The
input data, [8x1] column-vector, will
be loaded through DIN11-0 for Filter
A; either RIN11-0 or DIN11-0 can
be the data input for Filter B.
Conversely, when configured for a
[16x16][16x1] matrix-vector operation,
the coefficient banks will require 16
coefficient sets to be loaded into
the coefficient memory banks; each
coefficient set will have 16, 12-bit
coefficients. The input data, [16x1]
column-vector, will be loaded through
DIN11-0.
To configure the LF3320 for
F
Video Imaging Products
IGURE
R
R
R
R
0
1
2
i
=
7. M
C
C
C
C
C = COEFFICIENTS
D = DATA INPUT
R = DATA OUTPUT
00
10
20
i0
R
C
C
C
C
i
For j=0,1,2,...,(N-1)
01
11
21
i1
ATRIX
=
N=8 or 16
C
C
C
C
(N-1)
i=0
02
12
22
i2
C
E
6/22/2007–LDS.3320-R
ij
QUATION
C
C
C
C
D
0j
1j
2j
ij
i
LF3320
D
D
D
D
0
1
2
i