lf3320 LOGIC Devices Incorporated, lf3320 Datasheet - Page 11

• Manufacturer Part Number: lf3320
• Description: Horizontal Digital Image Filter
• Manufacturer: LOGIC Devices Incorporated

DEVICES INCORPORATED
not being read. The extra clock cycles
are used to calculate more filter taps.
When decimating, the I/D Registers
should be set to a length equal to the
decimation factor. For example, when
performing a 4:1 decimation, the
I/D Registers should be set to a
length of four. When decimation is
disabled or when only one data set
(non-interleaved data) is fed into the
device, the I/D Registers should be set
T
T
ABLE
ABLE
BITS
BITS
11-3
11-7
4-1
0
1
2
0
5
6
2. C
3. C
FUNCTION
ALU Mode Filter A
Pass A Filter A
Pass B Filter A
Reserved
FUNCTION
Filter A Odd-Tap
Interleave Mode
Filter A I/D Register Length
Filter A Tap Number
Filter A Data Reversal
Reserved
ONFIGURATION
ONFIGURATION
R
R
EGISTER
EGISTER
DESCRIPTION
0 : A + B
1 : B – A
0 : ALU Input A = 0
1 : ALU Input A = Forward Register Path
0 : ALU Input B = 0
1 : ALU Input B = Reverse Register Path
Should be set to “0”
DESCRIPTION
0 : Odd-Tap Interleave Mode Disabled
1 : Odd-Tap Interleave Mode Enabled
0000:
0001:
0010:
0011:
0100:
0101:
0110:
0111:
1000:
1001: 1
1010: 1
1011: 1
1100: 1
1101: 1
1110: 1
1111: 1
0 : Even Number of Taps
1 : Odd Number of Taps
0 : Data Reversal Enabled
1 : Data Reversal Disabled
Should be set to “0”
to a length of one.
I/D Register Data Path Control
The three multiplexers in the I/D
Register data path control how data
is routed through the forward and
reverse data paths.
The forward data path contains the
I/D Registers in which data flows
from left to right in the block diagram
in Figure 1. The reverse data path
contains the I/D Registers in which
0 – A
1 – A
DDRESS
DDRESS
1 Register
2 Registers
3 Registers
4 Registers
5 Registers
6 Registers
7 Registers
8 Registers
9 Registers
0 Registers
1 Registers
2 Registers
3 Registers
4 Registers
5 Registers
6 Registers
200H
201H
2-11
Horizontal Digital Image Filter
data flows from right to left.
In Single or Dual Filter Modes, data is
fed from the forward data path to the
reverse data path as follows. When
the filter is configured for an even
number of taps, data from the last
I/D Register in the forward data path
is fed into the first I/D Register in
the reverse data path (see Figure 13).
When the filter is configured for an
odd number of taps, the data which
will appear at the output of the last
I/D Register in the forward data path
on the next clock cycle is fed into the
first I/D Register in the reverse data
path. Bit 5 in Configuration Register
1 and Configuration Register 3 config-
ures Filters A and B respectively for an
even or odd number of taps.
When interleaved data is fed through
the device and an even tap filter is
desired, the filter should be config-
ured for an even number of taps and
the I/D Register length should match
the number of data sets interleaved
together. When interleaved data is fed
through the device and an odd tap
filter is desired, the filter should be set
to Odd-Tap Interleave Mode. Bit 0 of
Configuration Register 1 and Configu-
ration Register 3 configures Filters A
and B respectively for Odd-Tap Inter-
leave Mode. When the filter is con-
figured for Odd-Tap Interleave Mode,
data from the next to last I/D Register
in the forward data path is fed into the
first I/D Register in the reverse data
path.
When the filter is configured for an
odd number of taps (interleaved or
non-interleaved modes), the filter is
structured such that the center data
value is aligned simultaneously at the
A and B inputs of the last ALU in the
forward data path. In order to achieve
the correct result, the user must divide
the coefficient by two.
Data Reversal
Data reversal circuitry is placed after
the multiplexers which route data
from the forward data path to the
Video Imaging Products
6/22/2007–LDS.3320-R
LF3320