a3p250l Actel Corporation, a3p250l Datasheet
a3p250l
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a3p250l Summary of contents
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... High-Performance, Low-Skew Global Network • Architecture Supports Ultra-High Utilization Advanced and Pro (Professional) I/Os • 700 Mbps DDR, LVDS-Capable I/Os • 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation Table 1-1 • ProASIC3 Low-Power Product Family ProASIC3L Devices A3P250L 1 ARM Cortex-M1 Devices System Gates 250 k VersaTiles (D-flip-flops) 6,144 ...
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... Each used differential I/O pair reduces the number of single-ended I/Os available by two. 3. For A3P250L devices, the maximum number of LVPECL pairs in east and west banks cannot exceed 15. 4. FG256 and FG484 are footprint-compatible packages. ...
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... ProASIC3L Ordering Information _ A3P1000L 1 FG Package Type Speed Grade Blank = Standard 1 = 15% Faster than Standard Part Number ProASIC3L Devices A3P250L = 250,000 System Gates A3P600L = 600,000 System Gates A3P1000L = 1,000,000 System Gates A3PE3000L = 3,000,000 System Gates ProASIC3L Devices with Cortex-M1 M1A3P600L = 600,000 System Gates ...
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... Notes Commercial temperature range: 0°C to 70°C ambient temperature Industrial temperature range: –40°C to 85°C ambient temperature. Contact your local Actel representative for device availability: http://www.actel.com/contact/default.aspx A3P250L A3P600L M1A3P600L C, I – – ...
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ProASIC3L Device Family Overview General Description The ProASIC3L family of Actel flash FPGAs dramatically reduces dynamic power consumption by 40% and static power by 50%. These power savings are coupled with performance, density, true single-chip, 1 ...
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ProASIC3L Device Family Overview Flash Advantages Low Power The ProASIC3L family of Actel flash-based FPGAs provide a low-power advantage, and when coupled with high performance, enables designers to make power-smart choices using a single- chip, reprogrammable, and live-at-power-up device. ProASIC3L ...
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Reduced Cost of Ownership Advantages to the designer extend beyond low unit cost, performance, and ease of use. Unlike SRAM-based FPGAs, flash-based ProASIC3L devices allow all functionality to be live at power-up; no external boot PROM is required. On-board security ...
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... ProASIC3L Device Family Overview Bank 0 ISP AES User Nonvolatile Decryption* FlashRom Bank 2 Figure 1-1 • ProASIC3L Device Architecture Overview with Four I/O Banks (A3P250L, A3P600L, and A3P1000L) ISP AES User Nonvolatile Decryption* FlashRom Figure 1-2 • ProASIC3EL Device Architecture Overview 1 -4 Flash*Freeze Charge Technology ...
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Flash*Freeze Technology The ProASIC3L devices offer Actel's proven Flash*Freeze technology, which enables designers to instantaneously shut off dynamic power consumption while retaining all SRAM and register information. Flash*Freeze technology enables the user to quickly (within 1 µs) enter and exit ...
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ProASIC3L Device Family Overview User Nonvolatile FlashROM Actel ProASIC3L devices have 1 kbit of on-chip, user-accessible, nonvolatile FlashROM. The FlashROM can be used in diverse system applications: • Internet Protocol addressing (wireless or fixed) • System calibration settings • Device ...
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The inputs of the six CCC blocks are accessible from the FPGA core or from one of several inputs located near the CCC that have dedicated connections to the CCC block. The CCC block has these key features: • Wide ...
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... Reference to M1A3P250L was removed from (January 2008) Product Family, the Information" section, and the note regarding M1A3P250L was removed from the 1 -8 Changes in Current Version (v1.1) Table 1-1 · ProASIC3 Low-Power "I/Os Per Package1" table, the "ProASIC3L Ordering "Temperature Grade Offerings" ...
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ProASIC3L DC and Switching Characteristics General Specifications Operating Conditions Stresses beyond those listed in Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute Maximum Ratings are stress ratings only; functional operation of the ...
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ProASIC3L DC and Switching Characteristics Table 2-2 • Recommended Operating Conditions Symbol T Ambient temperature A T Junction Temperature 1.2 V–1.5 V wide range core voltage CC V JTAG DC voltage JTAG 4 V Programming voltage PUMP ...
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Table 2-4 • Overshoot and Undershoot Limits Average V –GND Overshoot or Undershoot CCI V Duration as a Percentage of Clock Cycle CCI 2 less 3 V 3.3 V 3.6 V Notes: 1. Based on reliability requirements at ...
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ProASIC3L DC and Switching Characteristics PLL Behavior at Brownout Condition Actel recommends using monotonic power supplies or voltage regulators to ensure proper powerup behavior. Power ramp-up should be monotonic at least until V brownout activation levels. The V and Figure ...
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CCI where VT can be from 0. 0.9 V (typically 0. 1.575 V CC Region 1: I/O Buffers are OFF Activation trip point: V ...
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... Device Pin Count Still Air 200 ft./min. 500 ft./min. jc All devices 100 10.0 35.3 All devices 208 8.0 26.1 All devices 208 3.8 16.2 A3P250L 144 12.2 43.8 A3P600L 144 8.3 35.8 A3P1000L 144 6.3 31.6 A3P250L 256 12.0 38.6 A3P600L 256 8.5 32.0 A3P1000L 256 6.6 28.1 AGLE3000 324 TBD TBD A3P600L 484 9.5 27.5 A3P1000L 484 8.0 23.3 A3PE3000L 484 4.7 20.6 A3PE3000L 896 2 ...
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... Characteristics, ProASIC3L Flash*Freeze Mode* DD A3P600L A3P1000L 0.33 0.55 0.88 , and V currents. Values do not include I/O static contribution (P CCPLL ) Characteristics, ProASIC3L Sleep Mode (V DD Core Voltage A3P250L A3P600L 1.2 V 1.7 1.7 1.2 V 1.8 1.8 1.2 V 1.9 1.9 1.2 V 2.2 2.2 1.2 V 2.5 2.5 currents. Values do not include I/O static contribution (P ) Characteristics, Shutdown Mode (V DD Core Voltage A3PE3000L 1 and V currents ...
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... Notes calculate total device I , multiply the number of banks used Includes and V CC CCPLL PUMP 3. Per bank. CCI JTAG 4. Values do not include I/O static contribution ( ProASIC3L Flash*Freeze Mode DD Core Voltage A3P250L A3P600L 1.2 V 0.33 0.55 1.2 V 1.7 1.7 1.2 V 1.8 1.8 1.2 V 1.9 1.9 1.2 V 2.2 2.2 1.2 V 2.5 2.5 CCI currents ...
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Power per I/O Pin Table 2-11 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings Applicable to Pro I/O Banks Single-Ended 3.3 V LVTTL/LVCMOS 3.3 V LVTTL/LVCMOS – Schmitt trigger 2.5 V LVCMOS 2.5 V ...
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ProASIC3L DC and Switching Characteristics Table 2-12 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings Applicable to Advanced I/O Banks Single-Ended 3.3 V LVTTL / 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS ...
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Table 2-14 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings Applicable to Pro I/Os Single-Ended 3.3 V LVTTL/LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS (JESD8-11) 1.2 V LVCMOS 3.3 V PCI ...
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ProASIC3L DC and Switching Characteristics Table 2-15 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings Applicable to Advanced I/O Banks Single-Ended 3.3 V LVTTL / 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS ...
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... A3PE3000L A3P1000L A3P600L A3P250L 12.61 2.66 0.56 VersaTile used as a See Table 2-11 on page See Table 2-14 on page 2-11 Device Specific Dynamic Power (µW) A3PE3000L A3P1000L A3P600L A3P250L See See See -dependent) See Table 2-7 on page CCI page See Table 2-11 on page 2-9 See Table 2-14 on page 2- ...
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ProASIC3L DC and Switching Characteristics Power Calculation Methodology This section describes a simplified method to estimate power consumption of an application. For more accurate and detailed power estimations, use the SmartPower tool in Actel Libero IDE software. The power calculation ...
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Combinatorial Cells Contribution—P α C-CELL C-CELL the number of VersaTiles used as combinatorial modules in the design. C-CELL α is the toggle rate of VersaTile outputs—guidelines are provided in ...
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ProASIC3L DC and Switching Characteristics Guidelines Toggle Rate Definition A toggle rate defines the frequency of a net or logic element relative to a clock percentage. If the toggle rate of a net is 100%, this means ...
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User I/O Characteristics Timing Model I/O Module (Registered 1. LVPECL D Q (Applicable to Advanced I/O Banks only 0.24 ns ICLKQ t = 0.26 ns ISUD Input LVTTL Clock Register Cell t = 0.76 ...
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ProASIC3L DC and Switching Characteristics t PY PAD DIN V PAD Y GND DIN GND Figure 2-4 • Input Buffer Timing Model and Delays (example CLK I/O Interface = MAX(t (R), t ...
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DOUT D Q CLK D From Array I/O Interface D DOUT PAD Figure 2-5 • Output Buffer Model and Delays (example) ProASIC3L DC and Switching Characteristics t DP DOUT t = MAX(t (R MAX(t ...
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ProASIC3L DC and Switching Characteristics t EOUT D Q CLK CLK D I/O Interface D 50 EOUT (R) 50% EOUT t ZL PAD V trip D 50 EOUT (R) 50% EOUT t ZLS ...
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Overview of I/O Performance Summary of I/O DC Input and Output Levels – Default I/O Software Settings Table 2-21 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and Industrial Conditions—Software Default Settings Applicable to ...
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ProASIC3L DC and Switching Characteristics Table 2-22 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and Industrial Conditions—Software Default Settings Applicable to Advanced I/O Banks Drive Slew I/O Standard Strength Rate 3.3 V LVTTL ...
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Table 2-24 • Summary of Maximum and Minimum DC Input Levels Applicable to Commercial and Industrial Conditions DC I/O Standard 3.3 V LVTTL / 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 1.2 V LVCMOS 3.3 ...
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ProASIC3L DC and Switching Characteristics Summary of I/O Timing Characteristics – Default I/O Software Settings Table 2-25 • Summary of AC Memory Points Input Reference Voltage Standard 3.3 V LVTTL / 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS ...
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Table 2-27 • Summary of I/O Timing Characteristics—Software Default Settings –1 Speed Grade, Commercial-Case Conditions: T Pro I/O Banks Standard 3.3 V LVTTL / 12 mA High 5 3.3 V LVCMOS 2.5 V LVCMOS 12 mA High 5 1.8 V ...
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ProASIC3L DC and Switching Characteristics Table 2-28 • Summary of I/O Timing Characteristics—Software Default Settings –1 Speed Grade, Commercial-Case Conditions: T Advanced I/O Banks I/O Standard 3.3 V LVTTL / 12 mA High 5pF 3.3 V LVCMOS 2.5 V LVCMOS ...
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Table 2-29 • Summary of I/O Timing Characteristics—Software Default Settings –1 Speed Grade, Commercial-Case Conditions: T Standard Plus I/O Banks I/O Standard 3.3 V LVTTL / 12 mA High 5pF 3.3 V LVCMOS 2.5 V LVCMOS 12 mA High 5pF ...
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ProASIC3L DC and Switching Characteristics Table 2-31 • I/O Output Buffer Maximum Resistances Applicable to Pro I/Os Standard 3.3 V LVTTL / 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 1.2 V LVCMOS 3.3 V PCI/PCI-X ...
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Table 2-32 • I/O Output Buffer Maximum Resistances Applicable to Advanced I/O Banks Standard 3.3 V LVTTL / 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 1.2 V LVCMOS 3.3 V PCI/PCI-X Notes: 1. These maximum ...
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ProASIC3L DC and Switching Characteristics Table 2-33 • I/O Output Buffer Maximum Resistances Applicable to Standard Plus I/O Banks Standard 3.3 V LVTTL / 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 1.2 V LVCMOS 3.3 ...
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Table 2-34 • I/O Weak Pull-Up/Pull-Down Resistances Minimum and Maximum Weak Pull-Up/Pull-Down Resistance Values R V Min. CCI 1.2 V LVCMOS TBD Notes: 1. ...
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ProASIC3L DC and Switching Characteristics Table 2-35 • I/O Short Currents I Applicable to Pro I/Os 3.3 V LVTTL / 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 1.2 V LVCMOS 3.3 V PCI/PCIX 3.3 V ...
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Table 2-36 • I/O Short Currents I /I OSH Applicable to Advanced I/O Banks 3.3 V LVTTL / 3.3 V LVCMOS 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 1.2 V LVCMOS 3.3 V PCI/PCI-X * ...
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ProASIC3L DC and Switching Characteristics Table 2-37 • I/O Short Currents I Applicable to Standard Plus I/O Banks 3.3 V LVTTL / 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 1.2 V LVCMOS 3.3 V PCI/PCI-X ...
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Table 2-39 • Short Current Event Duration before Failure Temperature –40°C 0°C 25°C 70°C 85°C 100°C 110°C Table 2-40 • I/O Input Rise Time, Fall Time, and Related I/O Reliability Input Buffer Input Rise/Fall Time (min.) LVTTL/LVCMOS No requirement LVDS/BLVDS/ ...
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ProASIC3L DC and Switching Characteristics Single-Ended I/O Characteristics 3.3 V LVTTL / 3.3 V LVCMOS Low-Voltage Transistor–Transistor Logic (LVTTL general-purpose standard (EIA/JESD) for 3.3 V applications. It uses an LVTTL input buffer and push-pull output buffer. Table 2-41 ...
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Table 2-43 • Minimum and Maximum DC Input and Output Levels Applicable to Standard Plus I/O Banks 3.3 V LVTTL / 3.3 V LVCMOS V IL Drive Strength Min., V Max., V Min., V Max., V Max., V Min., V ...
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ProASIC3L DC and Switching Characteristics Timing Characteristics Table 2-45 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew Commercial-Case Conditions: T Applicable to Pro I/Os Drive Speed Strength Grade t t DOUT Std. 0.77 5.48 –1 ...
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Table 2-47 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew Commercial-Case Conditions: T Applicable to Advanced I/Os Drive Speed Strength Grade t t DOUT Std. 0.70 5.11 –1 0.60 4. Std. 0.70 4.30 ...
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ProASIC3L DC and Switching Characteristics Table 2-49 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew Commercial-Case Conditions: T Applicable to Standard Plus I/Os Drive Speed Strength Grade t t DOUT 4 mA Std. 0.70 4.61 –1 0.60 3.92 ...
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V LVCMOS Low-Voltage CMOS for 2 extension of the LVCMOS standard (JESD8-5) used for general- purpose 2.5 V applications. It uses a 5 V–tolerant input buffer and push-pull output buffer. Table 2-51 • Minimum and Maximum ...
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ProASIC3L DC and Switching Characteristics Table 2-53 • Minimum and Maximum DC Input and Output Levels Applicable to Standard Plus I/O Banks 2.5 V LVCMOS V IL Drive Strength Min., V Max., V Min –0.3 0.7 4 ...
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Timing Characteristics Table 2-55 • 2.5 V LVCMOS Low Slew Commercial-Case Conditions: T Applicable to Pro I/Os Drive Speed Strength Grade DOUT Std. 0.77 6.24 0.05 –1 0.66 5.31 0. Std. 0.77 ...
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ProASIC3L DC and Switching Characteristics Table 2-57 • 2.5 V LVCMOS Low Slew Commercial-Case Conditions: T Applicable to Advanced I/Os Drive Speed Strength Grade t t DOUT 4 mA Std. 0.70 5.79 –1 0.60 4. Std. 0.70 4.84 ...
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Table 2-59 • 2.5 V LVCMOS Low Slew Commercial-Case Conditions: T Applicable to Standard Plus I/Os Drive Speed Strength Grade t t DOUT Std. 0.70 5.27 –1 0.60 4. Std. 0.70 4.32 –1 0.60 3.68 ...
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ProASIC3L DC and Switching Characteristics 1.8 V LVCMOS Low-voltage CMOS for 1 extension of the LVCMOS standard (JESD8-5) used for general- purpose 1.8 V applications. It uses a 1.8 V input buffer and a push-pull output buffer. ...
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Table 2-63 • Minimum and Maximum DC Input and Output Levels Applicable to Standard Plus I/O I/O Banks 1.8 V LVCMOS V IL Drive Strength Min., V Max., V Min –0 ...
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ProASIC3L DC and Switching Characteristics Timing Characteristics Table 2-65 • 1.8 V LVCMOS Low Slew Commercial-Case Conditions: T Applicable to Pro I/Os Drive Speed Strength Grade t t DOUT Std. 0.77 8.32 –1 0.66 7. ...
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Table 2-67 • 1.8 V LVCMOS Low Slew Commercial-Case Conditions: T Applicable to Advanced I/Os Drive Speed Strength Grade t t DOUT Std. 0.70 7.77 –1 0.60 6. Std. 0.70 6.38 –1 0.60 5.43 6 ...
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ProASIC3L DC and Switching Characteristics Table 2-69 • 1.8 V LVCMOS Low Slew Commercial-Case Conditions: T Applicable to Standard Plus I/Os Drive Speed Strength Grade t t DOUT 2 mA Std. 0.70 7.21 –1 0.60 6. Std. 0.70 ...
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V LVCMOS (JESD8-11) Low-Voltage CMOS for 1 extension of the LVCMOS standard (JESD8-5) used for general- purpose 1.5 V applications. It uses a 1.5 V input buffer and a push-pull output buffer. Table 2-71 • Minimum ...
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ProASIC3L DC and Switching Characteristics Table 2-73 • Minimum and Maximum DC Input and Output Levels Applicable to Standard Plus I/O Banks 1.5 V LVCMOS V IL Drive Strength Min., V Max., V Min –0.3 0.35 * ...
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Timing Characteristics Table 2-75 • 1.5 V LVCMOS Low Slew Commercial-Case Conditions: T Applicable to Pro I/Os Drive Speed Strength Grade DOUT Std. 0.77 8.65 0.05 –1 0.66 7.36 0. Std. 0.77 ...
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ProASIC3L DC and Switching Characteristics Table 2-77 • 1.5 V LVCMOS Low Slew Commercial-Case Conditions: T Applicable to Advanced I/Os Drive Speed Strength Grade t t DOUT 2 mA Std. 0.70 8.00 –1 0.60 6. Std. 0.70 6.91 ...
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Table 2-79 • 1.5 V LVCMOS Low Slew Commercial-Case Conditions: T Applicable to Standard Plus I/Os Drive Speed Strength Grade t t DOUT Std. 0.70 7.32 –1 0.60 6. Std. 0.70 6.29 –1 0.60 5.35 ...
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ProASIC3L DC and Switching Characteristics 1.2 V LVCMOS (JESD8-12A) Low-Voltage CMOS for 1.2 V complies with the LVCMOS standard JESD8-12A for general purpose 1.2 V applications. It uses a 1.2 V input buffer and a push-pull output buffer. Table 2-81 ...
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Test Point Datapath 5 pF Figure 2-11 • AC Loading Table 2-84 • AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) Input HIGH ( Measuring point = V See Table 2-25 on page 2-24 trip. ProASIC3L ...
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ProASIC3L DC and Switching Characteristics Timing Characteristics 1 Core Voltage. Table 2-85 • 1.2 V LVCMOS Low Slew Commercial-Case Conditions: T Applicable to Pro I/O Banks Drive Speed Strength Grade t t DOUT Std. 0.77 ...
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Table 2-89 • 1.2 V LVCMOS High Slew Commercial-Case Conditions: T Applicable to Standard Plus I/O Banks Drive Strength Speed Grade t DOUT 2 mA Std. 0.70 –1 0.60 Note: For specific junction temperature and voltage supply levels, refer to ...
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ProASIC3L DC and Switching Characteristics 3.3 V PCI, 3.3 V PCI-X Peripheral Component Interface for 3.3 V standard specifies support for 33 MHz and 66 MHz PCI Bus applications. Table 2-91 • Minimum and Maximum DC Input and Output Levels ...
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Timing Characteristics Table 2-93 • 3.3 V PCI/PCI-X Commercial-Case Conditions: T Applicable to Pro I/Os Speed Grade DOUT DP DIN Std. 0.77 2.52 0.05 –1 0.66 2.15 0.04 Note: For specific junction temperature and voltage supply levels, ...
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ProASIC3L DC and Switching Characteristics Voltage-Referenced I/O Characteristics 3.3 V GTL Gunning Transceiver Logic is a high-speed bus standard (JESD8-3). It provides a differential amplifier input buffer and an open-drain output buffer. The V 3.3 V. Table 2-96 • Minimum ...
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V GTL Gunning Transceiver Logic is a high-speed bus standard (JESD8-3). It provides a differential amplifier input buffer and an open-drain output buffer. The V 2.5 V Table 2-99 • Minimum and Maximum DC Input and Output Levels 2.5 ...
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ProASIC3L DC and Switching Characteristics 3.3 V GTL+ Gunning Transceiver Logic Plus is a high-speed bus standard (JESD8-3). It provides a differential amplifier input buffer and an open-drain output buffer. The V 3.3 V Table 2-102 • Minimum and Maximum ...
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V GTL+ Gunning Transceiver Logic Plus is a high-speed bus standard (JESD8-3). It provides a differential amplifier input buffer and an open-drain output buffer. The V 2.5 V. Table 2-105 • Minimum and Maximum DC Input and Output Levels ...
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ProASIC3L DC and Switching Characteristics HSTL Class I High-Speed Transceiver Logic is a general-purpose high-speed 1.5 V bus standard (EIA/JESD8-6). ProASIC3E devices support Class I. This provides a differential amplifier input buffer and a push-pull output buffer. Table 2-108 • ...
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HSTL Class II High-Speed Transceiver Logic is a general-purpose high-speed 1.5 V bus standard (EIA/JESD8-6). ProASIC3E devices support Class II. This provides a differential amplifier input buffer and a push- pull output buffer. Table 2-111 • Minimum and Maximum DC ...
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ProASIC3L DC and Switching Characteristics SSTL2 Class I Stub-Speed Terminated Logic for 2.5 V memory bus standard (JESD8-9). ProASIC3E devices support Class I. This provides a differential amplifier input buffer and a push-pull output buffer. Table 2-114 • Minimum and ...
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SSTL2 Class II Stub-Speed Terminated Logic for 2.5 V memory bus standard (JESD8-9). ProASIC3E devices support Class II. This provides a differential amplifier input buffer and a push-pull output buffer. Table 2-117 • Minimum and Maximum DC Input and Output ...
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ProASIC3L DC and Switching Characteristics SSTL3 Class I Stub-Speed Terminated Logic for 3.3 V memory bus standard (JESD8-8). ProASIC3E devices support Class I. This provides a differential amplifier input buffer and a push-pull output buffer. Table 2-120 • Minimum and ...
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SSTL3 Class II Stub-Speed Terminated Logic for 3.3 V memory bus standard (JESD8-8). ProASIC3E devices support Class II. This provides a differential amplifier input buffer and a push-pull output buffer. Table 2-123 • Minimum and Maximum DC Input and Output ...
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ProASIC3L DC and Switching Characteristics Differential I/O Characteristics Physical Implementation Configuration of the I/O modules as a differential pair is handled by Actel Designer software when the user instantiates a differential I/O macro in the design. Differential I/Os can also ...
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Table 2-126 • Minimum and Maximum DC Input and Output Levels DC Parameter Supply Voltage V CCI Output Low Voltage V OL Output High Voltage Output Lower Current Output High Current I OH Input ...
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ProASIC3L DC and Switching Characteristics BLVDS/M-LVDS Bus LVDS (BLVDS) and Multipoint LVDS (M-LVDS) specifications extend the existing LVDS standard to high-performance multipoint bus applications. Multidrop and multipoint bus configurations may contain any combination of drivers, receivers, and transceivers. Actel LVDS ...
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LVPECL Low-Voltage Positive Emitter-Coupled Logic (LVPECL) is another differential I/O standard. It requires that one data bit be carried through two signal lines. Like LVDS, two pins are needed. It also requires external resistor termination. The full implementation of the ...
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ProASIC3L DC and Switching Characteristics Timing Characteristics Table 2-132 • LVPECL Commercial-Case Conditions: T Applicable to Pro I/O Banks Speed Grade t DOUT Std. 0.77 –1 0.66 Note: For specific junction temperature and voltage supply levels, refer to values. Table ...
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I/O Register Specifications Fully Registered I/O Buffers with Synchronous Enable and Asynchronous Preset Preset PRE Data D C DFN1E1P1 E Enable B CLK A Data Input I/O Register with: Active High Enable Active High Preset Positive-Edge Triggered Figure 2-26 • ...
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ProASIC3L DC and Switching Characteristics Table 2-134 • Parameter Definition and Measuring Nodes Parameter Name t Clock-to-Q of the Output Data Register OCLKQ t Data Setup Time for the Output Data Register OSUD t Data Hold Time for the Output ...
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Fully Registered I/O Buffers with Synchronous Enable and Asynchronous Clear D Data CC DFN1E1C1 E Enable BB CLK AA CLR DD Data Input I/O Register with Active High Enable Active High Clear Positive-Edge Triggered Figure 2-27 • Timing Model of ...
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ProASIC3L DC and Switching Characteristics Table 2-135 • Parameter Definition and Measuring Nodes Parameter Name t Clock-to-Q of the Output Data Register OCLKQ t Data Setup Time for the Output Data Register OSUD t Data Hold Time for the Output ...
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Input Register 50% 50% CLK t ISUD 50% 1 Data Enable 50% t IHE t Preset ISUE Clear Out_1 Figure 2-28 • Input Register Timing Diagram Timing Characteristics Table 2-136 • Input Data Register Propagation Delays Commercial-Case Conditions: T Parameter ...
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ProASIC3L DC and Switching Characteristics Output Register 50% CLK 1 50% Data_out Enable 50% t OHE t Preset OSUE Clear DOUT Figure 2-29 • Output Register Timing Diagram Timing Characteristics Table 2-137 • Output Data Register Propagation Delays Commercial-Case Conditions: ...
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Output Enable Register 50% 50% CLK t OESUD 1 50% D_Enable 50% Enable t t OESUE OEHE Preset Clear EOUT t Figure 2-30 • Output Enable Register Timing Diagram Timing Characteristics Table 2-138 • Output Enable Register Propagation Delays Commercial-Case ...
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ProASIC3L DC and Switching Characteristics DDR Module Specifications Input DDR Module INBUF Data CLK CLKBUF CLR INBUF Figure 2-31 • Input DDR Timing Model Table 2-139 • Parameter Definitions Parameter Name t Clock-to-Out Out_QR DDRICLKQ1 t Clock-to-Out Out_QF DDRICLKQ2 t ...
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CLK Data 1 2 CLR t DDRIREMCLR t DDRICLR2Q1 Out_QF t DDRICLR2Q2 Out_QR Figure 2-32 • Input DDR Timing Diagram Timing Characteristics Table 2-140 • Input DDR Propagation Delays Commercial-Case Conditions: T Parameter t Clock-to-Out Out_QR for Input DDR DDRICLKQ1 ...
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ProASIC3L DC and Switching Characteristics Output DDR Module Data_F (from core) CLK CLKBUF Data_R (from core) CLR INBUF Figure 2-33 • Output DDR Timing Model Table 2-141 • Parameter Definitions Parameter Name t Clock-to-Out DDROCLKQ t Asynchronous Clear-to-Out DDROCLR2Q t ...
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CLK Data_F DDROREMCLR Data_R CLR DDROREMCLR t DDROCLR2Q Out Figure 2-34 • Output DDR Timing Diagram Timing Characteristics Table 2-142 • Output DDR Propagation Delays Commercial-Case Conditions: T Parameter t Clock-to-Out of DDR for ...
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ProASIC3L DC and Switching Characteristics VersaTile Characteristics VersaTile Specifications as a Combinatorial Module The ProASIC3 library offers all combinations of LUT-3 combinatorial functions. In this section, timing characteristics are presented for a sample of the library. For more details, refer ...
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50 50% OUT GND t PD (RR OUT t PD (RF) Figure 2-36 • Timing Model and Waveforms ProASIC3L DC and Switching ...
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ProASIC3L DC and Switching Characteristics Timing Characteristics Table 2-143 • Combinatorial Cell Propagation Delays Commercial-Case Conditions: T Combinatorial Cell INV AND2 NAND2 OR2 NOR2 XOR2 MAJ3 XOR3 MUX2 AND3 Note: For specific junction temperature and voltage supply levels, refer to ...
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CLK t SUD 50% Data EN 50 PRE SUE CLR Out t CLKQ Figure 2-38 • Timing Model and Waveforms Timing Characteristics Table 2-144 • Register Delays Commercial-Case Conditions: T Parameter t Clock-to-Q of the ...
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... Clock delays are device-specific. The global tree presented in device used to drive all D-flip-flops in the device. CCC Figure 2-39 • Example of Global Tree Use in an A3P250L Device for Clock Routing Figure 2- example of a global tree used for clock routing. Figure 2-39 is driven by a CCC located on the west side of the A3P250L ...
Page 105
... Conditioning Circuits" section on page Table 2-148 on page 2-94 present minimum and maximum global clock delays within each device. Minimum and maximum delays are measured with minimum and maximum loading. Timing Characteristics Table 2-145 • A3P250L Global Resource Commercial-Case Conditions: T Parameter Description t ...
Page 106
ProASIC3L DC and Switching Characteristics Table 2-147 • A3P1000L Global Resource Commercial-Case Conditions: T Parameter t Input LOW Delay for Global Clock RCKL t Input HIGH Delay for Global Clock RCKH t Minimum Pulse Width HIGH for Global Clock RCKMPWH ...
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Clock Conditioning Circuits CCC Electrical Specifications Timing Characteristics Table 2-149 • ProASIC3LP CCC/PLL Specification Parameter Clock Conditioning Circuitry Input Frequency f Clock Conditioning Circuitry Output Frequency f Delay Increments in Programmable Delay Blocks Number of Programmable Values in Each Programmable ...
Page 108
ProASIC3L DC and Switching Characteristics Output Signal Note: Peak-to-peak jitter measurements are defined by T Figure 2-40 • Peak-to-Peak Jitter Definition period_max period_min = T – T peak-to-peak period_max period_min ...
Page 109
Embedded SRAM and FIFO Characteristics SRAM ADDRA11 ADDRA10 ADDRA0 DINA8 DINA7 DINA0 WIDTHA1 WIDTHA0 PIPEA WMODEA BLKA WENA CLKA ADDRB11 ADDRB10 ADDRB0 DINB8 DINB7 DINB0 WIDTHB1 WIDTHB0 PIPEB WMODEB BLKB WENB CLKB Figure 2-41 • RAM Models ProASIC3L DC and ...
Page 110
ProASIC3L DC and Switching Characteristics Timing Waveforms CLK ADD t BKS BLK_B t ENS WEN_B Figure 2-42 • RAM Read for Pass-Through Output CLK ADD t BKS BLK_B t ENS WEN_B ...
Page 111
CYC t CKH CLK ADD 0 t BKS BLK_B t ENS WEN_B Figure 2-44 • RAM Write, Output Retained (WMODE = 0) t CKH CLK ...
Page 112
ProASIC3L DC and Switching Characteristics CLK1 ADD1 DI1 CLK2 WEN_B1 WEN_B2 ADD2 DI2 DO2 (pass-through) DO2 (pipelined) Figure 2-46 • Write Access after Write onto Same Address ...
Page 113
CLK1 ADD1 DI1 0 t WRO CLK2 WEN_B1 WEN_B2 A ADD2 DO2 D n (pass-through) DO2 D (pipelined) Figure 2-47 • Read Access after Write onto Same Address A ...
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ProASIC3L DC and Switching Characteristics CLK1 ADD1 WEN_B1 DO1 D n (pass-through) DO1 (pipelined) CLK2 ADD2 DI2 WEN_B2 Figure 2-48 • Write Access after Read onto Same Address CLK RESET_B Figure 2-49 • RAM Reset 2 -1 ...
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Timing Characteristics Table 2-150 • RAM4K9 Commercial-Case Conditions: T Parameter t Address setup time AS t Address hold time AH t REN_B, WEN_B setup time ENS t REN_B, WEN_B hold time ENH t BLK_B setup time BKS t BLK_B hold ...
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ProASIC3L DC and Switching Characteristics Table 2-151 • RAM512X18 Commercial-Case Conditions: T Parameter t Address setup time AS t Address hold time AH t REN_B, WEN_B setup time ENS t REN_B, WEN_B hold time ENH t Input data (DI) setup ...
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FIFO RW2 RW1 RW0 WW2 WW1 WW0 ESTOP FSTOP AEVAL11 AEVAL10 AEVAL0 AFVAL11 AFVAL10 AFVAL0 REN RBLK RCLK WD17 WD16 WD0 WEN WBLK WCLK RPIPE Figure 2-50 • FIFO Model ProASIC3L ...
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ProASIC3L DC and Switching Characteristics Timing Waveforms RCLK/ WCLK RESET_B EMPTY AEMPTY FULL AFULL WA/RA (Address Counter) Figure 2-51 • FIFO Reset RCLK EMPTY AEMPTY WA/RA NO MATCH (Address Counter) Figure 2-52 • FIFO EMPTY Flag and AEMPTY Flag Assertion ...
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WCLK FULL AFULL WA/RA NO MATCH (Address Counter) Figure 2-53 • FIFO FULL Flag and AFULL Flag Assertion WCLK MATCH WA/RA NO MATCH (EMPTY) (Address Counter) 1st Rising Edge After 1st Write RCLK EMPTY AEMPTY Figure 2-54 • FIFO EMPTY ...
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ProASIC3L DC and Switching Characteristics Timing Characteristics Table 2-152 • FIFO Worst Commercial-Case Conditions: T Parameter t REN_B, WEN_B Setup Time ENS t REN_B, WEN_B Hold Time ENH t BLK_B Setup Time BKS t BLK_B Hold Time BKH t Input ...
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Embedded FlashROM Characteristics t SU CLK t HOLD Address A 0 Data Figure 2-56 • Timing Diagram Timing Characteristics Table 2-153 • Embedded FlashROM Access Time Commercial-Case Conditions: T Parameter t Address Setup Time SU t Address Hold Time HOLD ...
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ProASIC3L DC and Switching Characteristics JTAG 1532 Characteristics JTAG timing delays do not include JTAG I/Os. To obtain complete JTAG timing, add I/O buffer delays to the corresponding standard selected; refer to the I/O timing characteristics in the Characteristics" section ...
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List of Changes The following table lists critical changes that were made in the current version of the chapter. Previous Version Advance v0 result of the Libero IDE v8.4 release, Actel now offers a wide range of core ...
Page 124
... The "1.2 V LVCMOS (JESD8-12A)" section Advance v0.1 The "PLL Behavior at Brownout Condition" section (January 2008) Table 2-145 · A3P250L Global Table 2-147 · A3P1000L Global Resource were updated with values for t The worst-case commercial conditions were added to FlashROM Access Table 2-17 · Different ...
Page 125
Actel Safety Critical, Life Support, and High-Reliability Applications Policy The Actel products described in this advance status datasheet may not have completed Actel’s qualification process. Actel may amend or enhance products during the product introduction and qualification process, resulting in ...
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...
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Package Pin Assignments 100-Pin VQFP 100 1 Note: This is the top view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx. 100-Pin VQFP v1.1 ProASIC3L Packaging ...
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... GDA1/IO60USB1 58 GDC0/IO58VDB1 59 GDC1/IO58UDB1 60 IO52NDB1 61 GCB2/IO52PDB1 62 GCA1/IO50PDB1 63 GCA0/IO50NDB1 64 GCC0/IO48NDB1 65 GCC1/IO48PDB1 CCI 67 GND IO43NDB1 70 GBC2/IO43PDB1 71 GBB2/IO42PSB1 72 IO41NDB1 v1.1 100-Pin VQFP Pin Number A3P250L Function 73 GBA2/IO41PDB1 74 VMV1 75 GNDQ 76 GBA1/IO40RSB0 77 GBA0/IO39RSB0 78 GBB1/IO38RSB0 79 GBB0/IO37RSB0 80 GBC1/IO36RSB0 81 GBC0/IO35RSB0 82 IO29RSB0 83 IO27RSB0 84 IO25RSB0 85 IO23RSB0 86 IO21RSB0 CCI 88 GND 89 V ...
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PQFP 208 1 Note: This is the top view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx. 208-Pin PQFP v1.1 ProASIC3L Packaging ...
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Package Pin Assignments 208-Pin PQFP Pin Number A3PL600 Function 1 GND 2 GAA2/IO174PDB3 3 IO174NDB3 4 GAB2/IO173PDB3 5 IO173NDB3 6 GAC2/IO172PDB3 7 IO172NDB3 8 IO171PDB3 9 IO171NDB3 10 IO170PDB3 11 IO170NDB3 12 IO169PDB3 13 IO169NDB3 14 IO168PDB3 15 IO168NDB3 16 ...
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PQFP Pin Number A3PL600 Function 109 TRST 110 V JTAG 111 GDA0/IO88NDB1 112 GDA1/IO88PDB1 113 GDB0/IO87NDB1 114 GDB1/IO87PDB1 115 GDC0/IO86NDB1 116 GDC1/IO86PDB1 117 IO84NDB1 118 IO84PDB1 119 IO82NDB1 120 IO82PDB1 121 IO81PSB1 122 GND 123 V B1 CCI 124 ...
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Package Pin Assignments 208-Pin PQFP Pin Number A3PL250 Function 1 GND 2 GAA2/IO118UDB3 3 IO118VDB3 4 GAB2/IO117UDB3 5 IO117VDB3 6 GAC2/IO116UDB3 7 IO116VDB3 8 IO115UDB3 9 IO115VDB3 10 IO114UDB3 11 IO114VDB3 12 IO113PDB3 13 IO113NDB3 14 IO112PDB3 15 IO112NDB3 16 ...
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PQFP Pin Number A3PL250 Function 109 TRST 110 V JTAG 111 GDA0/IO60VDB1 112 GDA1/IO60UDB1 113 GDB0/IO59VDB1 114 GDB1/IO59UDB1 115 GDC0/IO58VDB1 116 GDC1/IO58UDB1 117 IO57VDB1 118 IO57UDB1 119 IO56NDB1 120 IO56PDB1 121 IO55RSB1 122 GND 123 V B1 CCI 124 ...
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Package Pin Assignments 208-Pin PQFP Pin Number APL1000 Function 1 GND 2 GAA2/IO225PDB3 3 IO225NDB3 4 GAB2/IO224PDB3 5 IO224NDB3 6 GAC2/IO223PDB3 7 IO223NDB3 8 IO222PDB3 9 IO222NDB3 10 IO220PDB3 11 IO220NDB3 12 IO218PDB3 13 IO218NDB3 14 IO216PDB3 15 IO216NDB3 16 ...
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PQFP Pin Number APL1000 Function 109 TRST 110 V JTAG 111 GDA0/IO113NDB1 112 GDA1/IO113PDB1 113 GDB0/IO112NDB1 114 GDB1/IO112PDB1 115 GDC0/IO111NDB1 116 GDC1/IO111PDB1 117 IO109NDB1 118 IO109PDB1 119 IO106NDB1 120 IO106PDB1 121 IO104PSB1 122 GND 123 V B1 CCI 124 ...
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Package Pin Assignments 208-Pin PQFP Pin Number A3PE3000L Function 1 GND 2 GNDQ 3 VMV7 4 GAB2/IO308PSB7V4 5 GAA2/IO309PDB7V4 6 IO309NDB7V4 7 GAC2/IO307PDB7V4 8 IO307NDB7V4 9 IO303PDB7V3 10 IO303NDB7V3 11 IO299PDB7V3 12 IO299NDB7V3 13 IO295PDB7V2 14 IO295NDB7V2 15 IO291PSB7V2 16 ...
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PQFP Pin Number A3PE3000L Function 109 TRST 110 V JTAG 111 VMV3 112 GDA0/IO153NPB3V4 113 GDB0/IO152NPB3V4 114 GDA1/IO153PPB3V4 115 GDB1/IO152PPB3V4 116 GDC0/IO151NDB3V4 117 GDC1/IO151PDB3V4 118 IO134NDB3V2 119 IO134PDB3V2 120 IO132NDB3V2 121 IO132PDB3V2 122 GND 123 V B3 CCI 124 ...
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Package Pin Assignments 144-Pin FBGA 12 11 Note: This is the bottom view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx Ball Pad Corner ...
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... GFB0/IO109NPB3 F2 V COMPLF F3 GFB1/IO109PPB3 F4 IO107NPB3 F5 GND F6 GND F7 GND F8 GCC0/IO48NDB1 F9 GCB0/IO49NPB1 F10 GND F11 GCA1/IO50PDB1 F12 GCA2/IO51PDB1 v1.1 ProASIC3L Packaging 144-Pin FBGA Pin Number A3P250L Function G1 GFA1/IO108PPB3 G2 GND G3 V CCPLF G4 GFA0/IO108NPB3 G5 GND G6 GND G7 GND G8 GDC1/IO58UPB1 G9 IO53NDB1 G10 GCC2/IO53PDB1 G11 IO52NDB1 G12 GCB2/IO52PDB1 ...
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... Package Pin Assignments 144-Pin FBGA Pin Number A3P250L Function K1 GEB0/IO99NDB3 K2 GEA1/IO98PDB3 K3 GEA0/IO98NDB3 K4 GEA2/IO97RSB2 K5 IO90RSB2 K6 IO84RSB2 K7 GND K8 IO66RSB2 K9 GDC2/IO63RSB2 K10 GND K11 GDA0/IO60VDB1 K12 GDB0/IO59VDB1 L1 GND L2 VMV3 L3 FF/GEB2/IO96RSB2 L4 IO91RSB2 CCI L6 IO82RSB2 L7 IO80RSB2 L8 IO72RSB2 L9 TMS L10 V JTAG L11 VMV2 L12 TRST M1 GNDQ ...
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FBGA Pin Number A3P600L Function A1 GNDQ A2 VMV0 A3 GAB0/IO02RSB0 A4 GAB1/IO03RSB0 A5 IO10RSB0 A6 GND A7 IO34RSB0 IO50RSB0 A10 GBA0/IO58RSB0 A11 GBA1/IO59RSB0 A12 GNDQ B1 GAB2/IO173PDB3 B2 GND B3 GAA0/IO00RSB0 B4 GAA1/IO01RSB0 B5 ...
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Package Pin Assignments 144-Pin FBGA Pin Number A3P600L Function K1 GEB0/IO145NDB3 K2 GEA1/IO144PDB3 K3 GEA0/IO144NDB3 K4 GEA2/IO143RSB2 K5 IO119RSB2 K6 IO111RSB2 K7 GND K8 IO94RSB2 K9 GDC2/IO91RSB2 K10 GND K11 GDA0/IO88NDB1 K12 GDB0/IO87NDB1 L1 GND L2 VMV3 L3 FF/GEB2/IO142RSB2 L4 ...
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FBGA Pin Number A3P1000L Function A1 GNDQ A2 VMV0 A3 GAB0/IO02RSB0 A4 GAB1/IO03RSB0 A5 IO10RSB0 A6 GND A7 IO44RSB0 IO69RSB0 A10 GBA0/IO76RSB0 A11 GBA1/IO77RSB0 A12 GNDQ B1 GAB2/IO224PDB3 B2 GND B3 GAA0/IO00RSB0 B4 GAA1/IO01RSB0 B5 ...
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Package Pin Assignments 144-Pin FBGA Pin Number A3P1000L Function K1 GEB0/IO189NDB3 K2 GEA1/IO188PDB3 K3 GEA0/IO188NDB3 K4 GEA2/IO187RSB2 K5 IO169RSB2 K6 IO152RSB2 K7 GND K8 IO117RSB2 K9 GDC2/IO116RSB2 K10 GND K11 GDA0/IO113NDB1 K12 GDB0/IO112NDB1 L1 GND L2 VMV3 L3 FF/GEB2/IO186RSB2 L4 ...
Page 145
FBGA Note: This is the bottom view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx. A1 Ball Pad Corner ...
Page 146
... D14 GBB2/IO42PPB1 D15 NC D16 IO44NDB1 E1 IO113PDB3 IO116VDB3 E4 IO115UDB3 E5 VMV0 CCI CCI E8 IO19RSB0 v1.1 256-Pin FBGA Pin Number A3P250L Function E9 IO24RSB0 E10 V B0 CCI E11 V B0 CCI E12 VMV1 E13 GBC2/IO43PDB1 E14 IO46RSB1 E15 NC E16 IO45PDB1 F1 IO113NDB3 F2 IO112PPB3 IO115VDB3 ...
Page 147
... L11 GND L12 V B1 CCI L13 GDB0/IO59VPB1 L14 IO57VDB1 L15 IO57UDB1 L16 IO56PDB1 M1 IO103PDB3 IO101NPB3 M4 GEC0/IO100NPB3 v1.1 ProASIC3L Packaging 256-Pin FBGA Pin Number A3P250L Function M5 VMV3 CCI CCI IO74RSB2 M10 V B2 CCI M11 V B2 CCI M12 VMV2 M13 ...
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... R11 IO68RSB2 R12 IO65RSB2 R13 GDB2/IO62RSB2 R14 TDI R15 NC R16 TDO T1 GND T2 IO94RSB2 T3 FF/GEB2/IO96RSB2 T4 IO93RSB2 T5 IO90RSB2 T6 IO87RSB2 T7 IO83RSB2 T8 IO79RSB2 T9 IO78RSB2 T10 IO73RSB2 T11 IO70RSB2 T12 GDC2/IO63RSB2 256-Pin FBGA Pin Number A3P250L Function T13 IO67RSB2 T14 GDA2/IO61RSB2 T15 TMS T16 GND v1.1 ...
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FBGA Pin Number A3P600L Function A1 GND A2 GAA0/IO00RSB0 A3 GAA1/IO01RSB0 A4 GAB0/IO02RSB0 A5 IO11RSB0 A6 IO16RSB0 A7 IO18RSB0 A8 IO28RSB0 A9 IO34RSB0 A10 IO37RSB0 A11 IO41RSB0 A12 IO43RSB0 A13 GBB1/IO57RSB0 A14 GBA0/IO58RSB0 A15 GBA1/IO59RSB0 A16 GND B1 GAB2/IO173PDB3 ...
Page 150
Package Pin Assignments 256-Pin FBGA Pin Number A3P600L Function G13 GCC1/IO69PPB1 G14 IO65NPB1 G15 IO75PDB1 G16 IO75NDB1 H1 GFB0/IO163NPB3 H2 GFA0/IO162NDB3 H3 GFB1/IO163PPB3 H4 V COMPLF H5 GFC0/IO164NPB3 GND H8 GND H9 GND H10 GND H11 ...
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FBGA Pin Number A3P600L Function P9 IO107RSB2 P10 IO104RSB2 P11 IO97RSB2 P12 VMV1 P13 TCK P14 VPUMP P15 TRST P16 GDA0/IO88NDB1 R1 GEA1/IO144PDB3 R2 GEA0/IO144NDB3 R3 IO139RSB2 R4 GEC2/IO141RSB2 R5 IO132RSB2 R6 IO127RSB2 R7 IO121RSB2 R8 IO114RSB2 R9 IO109RSB2 ...
Page 152
Package Pin Assignments 256-Pin FBGA Pin Number A3P1000L Function A1 GND A2 GAA0/IO00RSB0 A3 GAA1/IO01RSB0 A4 GAB0/IO02RSB0 A5 IO16RSB0 A6 IO22RSB0 A7 IO28RSB0 A8 IO35RSB0 A9 IO45RSB0 A10 IO50RSB0 A11 IO55RSB0 A12 IO61RSB0 A13 GBB1/IO75RSB0 A14 GBA0/IO76RSB0 A15 GBA1/IO77RSB0 A16 ...
Page 153
FBGA Pin Number A3P1000L Function G13 GCC1/IO91PPB1 G14 IO90NPB1 G15 IO88PDB1 G16 IO88NDB1 H1 GFB0/IO208NPB3 H2 GFA0/IO207NDB3 H3 GFB1/IO208PPB3 H4 V COMPLF H5 GFC0/IO209NPB3 GND H8 GND H9 GND H10 GND H11 V CC H12 ...
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Package Pin Assignments 256-Pin FBGA Pin Number A3P1000L Function P9 IO137RSB2 P10 IO134RSB2 P11 IO128RSB2 P12 VMV1 P13 TCK P14 V PUMP P15 TRST P16 GDA0/IO113NDB1 R1 GEA1/IO188PDB3 R2 GEA0/IO188NDB3 R3 IO184RSB2 R4 GEC2/IO185RSB2 R5 IO168RSB2 R6 IO163RSB2 R7 IO157RSB2 ...
Page 155
FBGA Note: This is the bottom view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx. A1 Ball Pad Corner ...
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Package Pin Assignments 324-Pin FBGA Pin Number A3PE3000L Function A1 GND A2 IO08NDB0V0 A3 IO08PDB0V0 A4 IO10NDB0V1 A5 IO10PDB0V1 A6 IO12PDB0V1 A7 GND A8 IO32NDB0V3 A9 IO32PDB0V3 A10 IO42PPB1V0 A11 IO52NPB1V1 A12 GND A13 IO66NDB1V3 A14 IO72NDB1V3 A15 IO72PDB1V3 A16 ...
Page 157
FBGA Pin Number A3PE3000L Function F15 GBC2/IO84PDB2V0 F16 IO84NDB2V0 F17 IO92NDB2V1 F18 IO92PDB2V1 G1 GND G2 IO287PDB7V1 G3 IO287NDB7V1 G4 IO283PPB7V1 CCI G6 IO279PDB7V0 G7 IO291NPB7V2 IO26NDB0V3 G10 IO34NDB0V4 G11 V CC ...
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Package Pin Assignments 324-Pin FBGA Pin Number A3PE3000L Function M15 IO134NDB3V2 M16 IO134PDB3V2 M17 IO128PPB3V1 M18 GND N1 IO247NDB6V1 N2 IO247PDB6V1 N3 IO251NPB6V2 N4 GEC0/IO236NDB6V0 N5 V COMPLE N6 IO212NDB5V2 N7 IO212PDB5V2 N8 IO192NPB4V4 N9 IO174PDB4V2 N10 IO170PDB4V2 N11 GDA2/IO154PPB4V0 ...
Page 159
FBGA Pin Number A3PE3000L Function V10 IO182PPB4V3 V11 IO180PPB4V3 V12 GND V13 IO162NDB4V1 V14 IO160NDB4V0 V15 IO160PDB4V0 V16 IO158NDB4V0 V17 IO158PDB4V0 V18 GND v1.1 ProASIC3L Packaging ...
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Package Pin Assignments 484-Pin FBGA Note: This is the bottom view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx Ball Pad Corner ...
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FBGA Pin Number A3P600L Function A1 GND A2 GND CCI IO09RSB0 A7 IO15RSB0 A10 IO22RSB0 A11 IO23RSB0 A12 IO29RSB0 A13 IO35RSB0 A14 NC A15 NC A16 IO46RSB0 ...
Page 162
Package Pin Assignments 484-Pin FBGA Pin Number A3P600L Function C21 NC C22 V B1 CCI GND D5 GAA0/IO00RSB0 D6 GAA1/IO01RSB0 D7 GAB0/IO02RSB0 D8 IO11RSB0 D9 IO16RSB0 D10 IO18RSB0 D11 IO28RSB0 D12 IO34RSB0 D13 ...
Page 163
FBGA Pin Number A3P600L Function H19 IO66PDB1 H20 V CC H21 NC H22 IO166NDB3 J5 IO168NPB3 J6 IO167PPB3 J7 IO169PDB3 CCI J9 GND J10 V CC J11 V ...
Page 164
Package Pin Assignments 484-Pin FBGA Pin Number A3P600L Function N17 IO80NPB1 N18 IO74NPB1 N19 IO72NDB1 N20 NC N21 IO79NPB1 N22 IO153PDB3 P3 IO153NDB3 P4 IO159NDB3 P5 IO156NPB3 P6 IO151PPB3 P7 IO158PPB3 CCI P9 ...
Page 165
FBGA Pin Number A3P600L Function V15 IO96RSB2 V16 GDB2/IO90RSB2 V17 TDI V18 GNDQ V19 TDO V20 GND V21 NC V22 IO148PDB3 GND W5 IO137RSB2 W6 FF/GEB2/IO142RSB2 W7 IO134RSB2 W8 IO125RSB2 W9 IO123RSB2 ...
Page 166
Package Pin Assignments 484-Pin FBGA Pin Number A3P1000L Function A1 GND A2 GND CCI A4 IO07RSB0 A5 IO09RSB0 A6 IO13RSB0 A7 IO18RSB0 A8 IO20RSB0 A9 IO26RSB0 A10 IO32RSB0 A11 IO40RSB0 A12 IO41RSB0 A13 IO53RSB0 A14 IO59RSB0 A15 ...
Page 167
FBGA Pin Number A3P1000L Function C21 NC C22 V B1 CCI D1 IO219PDB3 D2 IO220NDB3 GND D5 GAA0/IO00RSB0 D6 GAA1/IO01RSB0 D7 GAB0/IO02RSB0 D8 IO16RSB0 D9 IO22RSB0 D10 IO28RSB0 D11 IO35RSB0 D12 IO45RSB0 D13 IO50RSB0 D14 IO55RSB0 ...
Page 168
Package Pin Assignments 484-Pin FBGA Pin Number A3P1000L Function H19 IO87PDB1 H20 V CC H21 NC H22 NC J1 IO212NDB3 J2 IO212PDB3 IO217NDB3 J5 IO218NDB3 J6 IO216PDB3 J7 IO216NDB3 CCI J9 GND J10 V ...
Page 169
FBGA Pin Number A3P1000L Function N17 IO100NPB1 N18 IO102NDB1 N19 IO102PDB1 N20 NC N21 IO101NPB1 N22 IO103PDB1 IO199PDB3 P3 IO199NDB3 P4 IO202NDB3 P5 IO202PDB3 P6 IO196PPB3 P7 IO193PPB3 CCI P9 GND P10 V ...
Page 170
Package Pin Assignments 484-Pin FBGA Pin Number A3P1000L Function V15 IO125RSB2 V16 GDB2/IO115RSB2 V17 TDI V18 GNDQ V19 TDO V20 GND V21 NC V22 IO109NDB1 IO191PDB3 GND W5 IO183RSB2 W6 FF/GEB2/IO186RSB2 W7 IO172RSB2 W8 ...
Page 171
FBGA Pin Number A3PE3000L Function A1 GND A2 GND CCI A4 IO10NDB0V1 A5 IO10PDB0V1 A6 IO16NDB0V1 A7 IO16PDB0V1 A8 IO18PDB0V2 A9 IO24PDB0V2 A10 IO28NDB0V3 A11 IO28PDB0V3 A12 IO46PDB1V0 A13 IO54PDB1V1 A14 IO56NDB1V1 A15 IO56PDB1V1 A16 IO64NDB1V2 ...
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Package Pin Assignments 484-Pin FBGA Pin Number A3PE3000L Function C21 IO94PPB2V1 C22 V B2 CCI D1 IO293PDB7V2 D2 IO303NDB7V3 D3 IO305NDB7V3 D4 GND D5 GAA0/IO00NDB0V0 D6 GAA1/IO00PDB0V0 D7 GAB0/IO01NDB0V0 D8 IO20PDB0V2 D9 IO22PDB0V2 D10 IO30PDB0V3 D11 IO38NDB0V4 D12 IO52NDB1V1 D13 ...
Page 173
FBGA Pin Number A3PE3000L Function H19 IO100PDB2V2 H20 V CC H21 VMV2 H22 IO105PDB2V2 J1 IO285NDB7V1 J2 IO285PDB7V1 J3 VMV7 J4 IO279PDB7V0 J5 IO283PDB7V1 J6 IO281PDB7V0 J7 IO287NDB7V1 CCI J9 GND J10 V CC J11 V ...
Page 174
Package Pin Assignments 484-Pin FBGA Pin Number A3PE3000L Function N17 IO132NPB3V2 N18 IO117NPB3V0 N19 IO132PPB3V2 N20 GNDQ N21 IO126NDB3V1 N22 IO128PDB3V1 P1 IO247PDB6V1 P2 IO253PDB6V2 P3 IO270NPB6V4 P4 IO261NPB6V3 P5 IO249PPB6V1 P6 IO259PDB6V3 P7 IO259NDB6V3 CCI P9 ...
Page 175
FBGA Pin Number A3PE3000L Function V15 IO155NDB4V0 V16 GDB2/IO155PDB4V0 V17 TDI V18 GNDQ V19 TDO V20 GND V21 IO146PDB3V4 V22 IO142NDB3V3 W1 IO239NDB6V0 W2 IO237PDB6V0 W3 IO230PSB5V4 W4 GND W5 IO232NDB5V4 W6 FF/GEB2/IO232PDB5 V4 W7 IO231NDB5V4 W8 IO214NDB5V2 W9 ...
Page 176
Package Pin Assignments 896-Pin FBGA Note: This is the bottom view. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx ...
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FBGA Pin Number A3PE3000L Function A2 GND A3 GND A4 IO14NPB0V1 A5 GND A6 IO07NPB0V0 A7 GND A8 IO09NDB0V1 A9 IO17NDB0V2 A10 IO17PDB0V2 A11 IO21NDB0V2 A12 IO21PDB0V2 A13 IO33NDB0V4 A14 IO33PDB0V4 A15 IO35NDB0V4 A16 IO35PDB0V4 A17 IO41NDB1V0 A18 IO43NDB1V0 ...
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Package Pin Assignments 896-Pin FBGA Pin Number A3PE3000L Function AC21 IO164PDB4V1 AC22 IO162PPB4V1 AC23 GND AC24 V COMPLD AC25 IO150NDB3V4 AC26 IO148NDB3V4 AC27 GDA1/IO153PDB3V4 AC28 IO145NDB3V3 AC29 IO143NDB3V3 AC30 IO137NDB3V2 AD1 GND AD2 IO242NPB6V1 AD3 IO240NDB6V0 AD4 GEC0/IO236NDB6V0 AD5 V ...
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FBGA Pin Number A3PE3000L Function AG5 IO220PPB5V3 AG6 IO228PDB5V4 AG7 IO231NDB5V4 AG8 GEC2/IO231PDB5V4 AG9 IO225NPB5V3 AG10 IO223NPB5V3 AG11 IO221PDB5V3 AG12 IO221NDB5V3 AG13 IO205NPB5V1 AG14 IO199NDB5V0 AG15 IO199PDB5V0 AG16 IO187NDB4V4 AG17 IO187PDB4V4 AG18 IO181NDB4V3 AG19 IO171PPB4V2 AG20 IO165NPB4V1 AG21 IO161NPB4V0 ...
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Package Pin Assignments 896-Pin FBGA Pin Number A3PE3000L Function AK23 IO169PDB4V1 AK24 GND AK25 IO167PPB4V1 AK26 GND AK27 GDC2/IO156PPB4V0 AK28 GND AK29 GND B1 GND B2 GND B3 GAA2/IO309PPB7V4 IO14PPB0V1 IO07PPB0V0 B8 ...
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FBGA Pin Number A3PE3000L Function E12 IO13PDB0V1 E13 IO34NDB0V4 E14 IO34PDB0V4 E15 IO40NDB0V4 E16 IO49NDB1V1 E17 IO49PDB1V1 E18 IO50PDB1V1 E19 IO58PDB1V2 E20 IO60NDB1V2 E21 IO77PDB1V4 E22 IO68NDB1V3 E23 IO68PDB1V3 E24 V B1 CCI E25 IO74PDB1V4 E26 V CC E27 ...
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Package Pin Assignments 896-Pin FBGA Pin Number A3PE3000L Function H26 IO84NDB2V0 H27 IO96PDB2V1 H28 IO96NDB2V1 H29 IO89PDB2V0 H30 IO89NDB2V0 J1 IO290NDB7V2 J2 IO290PDB7V2 J3 IO302NDB7V3 J4 IO302PDB7V3 J5 IO295NDB7V2 J6 IO299NDB7V3 CCI J8 V CCPLA J9 V ...
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FBGA Pin Number A3PE3000L Function M14 GND M15 GND M16 GND M17 GND M18 GND M19 GND M20 V CC M21 V B2 CCI M22 NC M23 IO104PPB2V2 M24 IO102PDB2V2 M25 IO102NDB2V2 M26 IO95PDB2V1 M27 IO97NDB2V1 M28 IO101NDB2V2 M29 ...
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Package Pin Assignments 896-Pin FBGA Pin Number A3PE3000L Function T2 V CCPLF T3 GFA2/IO272PPB6V4 T4 GFA1/IO273PDB6V4 T5 IO272NPB6V4 T6 IO267NDB6V4 T7 IO267PDB6V4 T8 IO265PDB6V3 T9 IO263PDB6V3 T10 V B6 CCI T11 V CC T12 GND T13 GND T14 GND T15 ...
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FBGA Pin Number A3PE3000L Function W20 V CC W21 V B3 CCI W22 IO134PDB3V2 W23 IO138PDB3V3 W24 IO132NDB3V2 W25 IO136NPB3V2 W26 IO130NPB3V2 W27 IO141PDB3V3 W28 IO135PDB3V2 W29 IO131PDB3V2 W30 IO123NDB3V1 Y1 IO266PDB6V4 Y2 IO250PDB6V2 Y3 IO250NDB6V2 Y4 IO246PDB6V1 Y5 ...
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Package Pin Assignments Part Number and Revision Date Part Number 51700100-003-1 Revised April 2008 List of Changes The following table lists critical changes that were made in the current version of the chapter. Previous Version v1.0 The "324-Pin FBGA" (January ...
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... Datasheet Categories Categories In order to provide the latest information to designers, some datasheets are published before data has been fully characterized. Datasheets are designated as “Product Brief,” “Advance,” and “Production”. The definition of these categories are as follows: Product Brief The product brief is a summarized version of a datasheet (advance or production) and contains general product information ...
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... Actel and the Actel logo are registered trademarks of Actel Corporation. All other trademarks are the property of their owners. Actel Corporation Actel Europe Ltd. 2061 Stierlin Court River Court,Meadows Business Park Mountain View, CA Station Approach, Blackwater 94043-4655 USA Camberley Surrey GU17 9AB United Kingdom Phone 650 ...