a3p250l Actel Corporation, a3p250l Datasheet - Page 87

• Manufacturer Part Number: a3p250l
• Description: Proasic3l Low-power Flash Fpgas With Flash*freeze Technology
• Manufacturer: Actel Corporation

Figure 2-25 • LVPECL Circuit Diagram and Board-Level Implementation
Table 2-130 • Minimum and Maximum DC Input and Output Levels
Table 2-131 • AC Waveforms, Measuring Points, and Capacitive Loads
OUTBUF_LVPECL
DC Parameter
V
V
V
V
V
V
V
V
Input LOW (V)
1.64
*
CCI
OL
OH
IL
ODIFF
OCM
ICM
IDIFF
Measuring point = V
, V
IH
LVPECL
Low-Voltage Positive Emitter-Coupled Logic (LVPECL) is another differential I/O standard. It
requires that one data bit be carried through two signal lines. Like LVDS, two pins are needed. It
also requires external resistor termination.
The full implementation of the LVDS transmitter and receiver is shown in an example in
Figure
receiver macro, three board resistors at the transmitter end, and one resistor at the receiver end.
The values for the three driver resistors are different from those used in the LVDS implementation
because the output standard specifications are different.
Supply Voltage
Output LOW Voltage
Output HIGH Voltage
Input LOW, Input HIGH Voltages
Differential Output Voltage
Output Common-Mode Voltage
Input Common-Mode Voltage
Input Differential Voltage
2-25. The building blocks of the LVPECL transmitter-receiver are one transmitter macro, one
FPGA
trip.
See
Description
Table 2-25 on page 2-24
N
P
Bourns Part Number: CAT16-PC4F12
100 Ω
100 Ω
Input HIGH (V)
A dv a n c e v 0. 4
187 W
1.94
0.625
1.762
Min.
0.96
1.01
300
1.8
for a complete table of trip points.
0
Z
Z
0
0
3.0
= 50 Ω
= 50 Ω
Max.
1.27
2.11
0.97
1.98
2.57
3.3
100 Ω
0.625
1.762
Min.
1.06
1.92
1.01
300
0
ProASIC3L DC and Switching Characteristics
3.3
N
P
Max.
1.43
2.57
2.28
0.97
1.98
3.6
Measuring Point* (V)
FPGA
+
–
0.625
1.762
Min.
Cross point
1.30
2.13
1.01
300
0
3.6
INBUF_LVPECL
Max.
1.57
2.41
0.97
1.98
2.57
3.9
Units
mV
V
V
V
V
V
V
V
2 - 75