a3p250l Actel Corporation, a3p250l Datasheet - Page 94

• Manufacturer Part Number: a3p250l
• Description: Proasic3l Low-power Flash Fpgas With Flash*freeze Technology
• Manufacturer: Actel Corporation

ProASIC3L DC and Switching Characteristics
Figure 2-29 • Output Register Timing Diagram
Table 2-137 • Output Data Register Propagation Delays
2 -8 2
Enable
CLK
Preset
Clear
DOUT
Data_out
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Note:
OCLKQ
OSUD
OHD
OSUE
OHE
OCLR2Q
OPRE2Q
OREMCLR
ORECCLR
OREMPRE
ORECPRE
OWCLR
OWPRE
OCKMPWH
OCKMPWL
For specific junction temperature and voltage supply levels, refer to
values.
Output Register
Timing Characteristics
Clock-to-Q of the Output Data Register
Data Setup Time for the Output Data Register
Data Hold Time for the Output Data Register
Enable Setup Time for the Output Data Register
Enable Hold Time for the Output Data Register
Asynchronous Clear-to-Q of the Output Data Register
Asynchronous Preset-to-Q of the Output Data Register
Asynchronous Clear Removal Time for the Output Data Register
Asynchronous Clear Recovery Time for the Output Data Register
Asynchronous Preset Removal Time for the Output Data Register
Asynchronous Preset Recovery Time for the Output Data Register
Asynchronous Clear Minimum Pulse Width for the Output Data Register
Asynchronous Preset Minimum Pulse Width for the Output Data Register
Clock Minimum Pulse Width HIGH for the Output Data Register
Clock Minimum Pulse Width LOW for the Output Data Register
Commercial-Case Conditions: T
50%
50%
t
1
OSUE
t
OHE
50%
50%
t
OSUD
0
t
t
OHD
OCLKQ
50%
J
50%
= 70°C, Worst-Case V
Description
50%
t
A d v a n c e v 0. 4
OWPRE
t
OPRE2Q
50%
50%
t
t
ORECPRE
50%
OCLR2Q
50%
t
OWCLR
50%
50%
CC
50%
= 1.14 V
t
ORECCLR
Table 2-6 on page 2-7
50%
t
OCKMPWH
t
50%
OREMPRE
0.78 0.92
0.42 0.49
0.00 0.00
0.58 0.69
0.00 0.00
1.07 1.26
1.07 1.26
0.00 0.00
0.30 0.35
0.00 0.00
0.30 0.35
0.19 0.22
0.19 0.22
0.31 0.36
0.28 0.32
t
50%
OCKMPWL
–1
for derating
Std. Units
t
OREMCLR
50%
50%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns