a3p250l Actel Corporation, a3p250l Datasheet - Page 97

• Manufacturer Part Number: a3p250l
• Description: Proasic3l Low-power Flash Fpgas With Flash*freeze Technology
• Manufacturer: Actel Corporation

Out_QR
Figure 2-32 • Input DDR Timing Diagram
Table 2-140 • Input DDR Propagation Delays
Out_QF
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
F
Note:
DDRICLKQ1
DDRICLKQ2
DDRISUD1
DDRISUD2
DDRIHD1
DDRIHD2
DDRICLR2Q1
DDRICLR2Q2
DDRIREMCLR
DDRIRECCLR
DDRIWCLR
DDRICKMPWH
DDRICKMPWL
DDRIMAX
Data
CLK
CLR
For specific junction temperature and voltage supply levels, refer to
values.
Timing Characteristics
Commercial-Case Conditions: T
t
t
1
Clock-to-Out Out_QR for Input DDR
Clock-to-Out Out_QF for Input DDR
Data Setup for Input DDR (fall)
Data Setup for Input DDR (rise)
Data Hold for Input DDR (fall)
Data Hold for Input DDR (rise)
Asynchronous Clear-to-Out Out_QR for Input DDR
Asynchronous Clear-to-Out Out_QF for Input DDR
Asynchronous Clear Removal Time for Input DDR
Asynchronous Clear Recovery Time for Input DDR
Asynchronous Clear Minimum Pulse Width for Input DDR
Clock Minimum Pulse Width HIGH for Input DDR
Clock Minimum Pulse Width LOW for Input DDR
Maximum Frequency for Input DDR
DDRICLR2Q1
DDRICLR2Q2
t
DDRIREMCLR
2
3
t
DDRICLKQ1
J
= 70°C, Worst-Case V
Description
4
A dv a n c e v 0. 4
2
3
5
CC
t
DDRICLKQ2
t
= 1.14 V
DDRISUD
6
ProASIC3L DC and Switching Characteristics
4
Table 2-6 on page 2-7
5
7
t
DDRIHD
0.43
0.61
0.44
0.39
0.00
0.00
0.73
0.89
0.00
0.35
0.22
0.36
0.32
TBD
–1
t
8
DDRIRECCLR
6
7
0.37
0.52
0.38
0.33
0.00
0.00
0.62
0.76
0.00
0.30
0.19
0.31
0.28
TBD
Std.
for derating
9
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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