afbr-820bz Avago Technologies, afbr-820bz Datasheet - Page 12

• Manufacturer Part Number: afbr-820bz
• Description: Twelve-channel Transmitter And Receiver Pluggable, Parallel-fiber-optic Modules
• Manufacturer: Avago Technologies

Control Characteristics: Transmitter/Receiver
The following characteristics are defined over the Recommended Operating Conditions unless otherwise noted. Typical
values are for Tc = 40°C, Vcc33 = 3.3 V and Vcc25 = 2.5 V.
Notes:
*
1. This is the module response time from a change in module address, Adr[2:0], to response to TWS communication using the new address.
2. This is the module response time from occurrence of interrupt generating event to IntL assertion, Vout:IntL = Vol.
3. Pulse or static level can be selected for IntL. Pulse mode is default. See Memory Map.
4. This is the module response time from clear on read operation, measured from falling SCL edge after stop bit of read transaction, until Vout:IntL =
5. Assertion of ResetL activates a complete module reset, i.e. module returns to factory default and non-volatile control settings. While ResetL is Low,
6. This is the response time from ResetL de-assertion to resumption of operation.
7. Data In Set Up Time is measured from Vil(max)SDA or Vih(min)SDA to Vil(max)SCL.
8. Data In Hold Time is measured from Vil(max)SCL to Vil(max)SDA or Vih(min)SDA.
9. Clock Low to Data Out Time is measured from Vil(max)SCL to Vol(max)SDA or Voh(min)SDA.
10. Data Out Hold Time is measured from Vil(max)SCL to Vol(max)SDA or Voh(min)SDA.
12
Parameter
Control* Input Voltage Hysteresis LVTTL
Control* Input Current LVTTL
Control* Output Voltage Low LVTTL
Control* Output Current High-Z
Address Assert Time
Interrupt Assert Time
Interrupt Pulse Width
Interrupt De-assert Time
Reset Assert Time
Reset De-assert Time
Initialization Time TWS Interfaces
TWS Data In Set Up Time
TWS Data In Hold Time
TWS Clock Low to Data Out Valid
TWS Data Out Hold Time
TWS Data Output Rise Time
TWS Data Output Fall Time
TWS Interface Timing
TWS Write Cycle Time
Control signals include Adr[2:0], IntL, ResetL, SCL and SDA.
Voh where IntL is in static mode.
Tx and Rx outputs are disabled and the module does not respond to the TWS interface.
Symbol
Vhys
Iin
Vol
Ioh
t
t
t
t
t
t
t
t
t
tr
tf
t
INTL ON
INTL PW
INTL OFF
RSTL ON
RSTL OFF
SU:SDA
HD:SDA
AA
DH
wr
SDA
SDA
Min
-125
-10
5
0.10
50
40ms
Typ
0.4
Max
0.4
100
200
500
100
500
500
0.10
0
0.90
0.30
0.30
125
10
Units
V
PA
V
PA
ms
ms
Ps
Ps
Ps
ms
ms
Ps
Ps
Ps
ns
Ps
Ps
Reference
0 V < Vin < Vcc33
Iol = 2mA
0 V < Vin < Vcc33
1
2, Figure 20
3, Figure 20
4, Figure 20
5, Figure 19
6, Figure 19
Figure 18
7, Figure 17
8, Figure 17
9, Figure 17
10, Figure 17
Figure 17,
Measured
between 0.8V
and 2.0V
See Atmel
Two-Wire
Serial EEPROM,
e.g. AT24C01A