afbr-820bz Avago Technologies, afbr-820bz Datasheet - Page 9

• Manufacturer Part Number: afbr-820bz
• Description: Twelve-channel Transmitter And Receiver Pluggable, Parallel-fiber-optic Modules
• Manufacturer: Avago Technologies

Recommended Operating Conditions
Recommended Operating Conditions specify parameters for which the optical and electrical characteristics hold
unless otherwise noted. Optical and electrical characteristics are not defined for operation outside the Recommended
Operating Conditions, reliability is not implied and damage to the module may occur for such operation over an
extended period of time.
Notes:
*
1. The position for case temperature measurement is shown in Figure 11. Continuous operation at the maximum Recommended Operating Case
2. While operation for various codes, e.g. 8b10b and 64b66b, are supported, certain parameters, jitter and sensitivity, are defined for specific operating
3. Data inputs are CML compatible. Minimum input requirement holds for default input equalization settings. Data Input Differential Peak to Peak
4. Data Input Common Mode Voltage is defined as follows: V
5. Deterministic Jitter, DJ, conforms to the dual-Dirac model where TJ(BER) = DJ + 2Q(BER)RJrms and RJrms is the width of the Gaussian component.
6. Total Jitter, TJ, defined for a BER of 10
7. Power Supply Noise is defined as the peak-to-peak noise amplitude over the frequency range at the host supply side of the recommended power
8. For data patterns with restricted run lengths and disparity, e.g. 8b10b, smaller value capacitors may provide acceptable results.
9. Channel insertion loss includes 3.5 dB/km attenuation, 0 dB connector loss and 0.3 dB modal noise penalty allocations.
9
Parameter
Case Temperature
2.5 V Power Supply Voltage
3.3 V Power Supply Voltage
Signal Rate per Channel
Data Input Differential Peak-to-Peak
Voltage Swing
Data Input Common Mode Voltage
Data Input Rise & Fall Times (20% - 80%)
Data Input Deterministic Jitter
Data Input Total Jitter
Control* Input Voltage High
Control* Input Voltage Low
Two Wire Serial Interface Clock Rate
Two Wire Serial Interface Write Cycle Time
Reset Pulse Width
Power Supply Noise
Receiver Differential Data Output Load
AC Coupling Capacitors – Receiver Data
Outputs
Fiber Length: 2000 MHz·km 50Pm MMF
Control signals, LVTTL (3.3 V) compatible, include Adr[2:0], IntL, ResetL, SCL and SDA.
Temperature should be avoided in order not to degrade reliability. Modules will function (degraded performance may result) where operated with
case temperatures below the minimum Recommended Operating Case Temperature.
conditions of 10 GBd and 8b/10b equivalent test patterns. The receiver has a low frequency -3dB (electrical) corner near 100 kHz.
Voltage Swing is defined as follows: 'V
Differential Data Input Voltage.
Here BER = 10
the measurement. All channels not under test are operating with similar test patterns.
operating at 10 GBd. Effects of impairments in the test signals due to the test system are removed from the measurement. All channels not under
test are operating with similar test patterns.
supply filter with the module and recommended filter in place. Voltage levels including peak-to-peak noise are limited to the recommended
operating range of the associated power supply. See Figures 12 and 13 for recommended power supply filters.
-12
. DJ is measured with the same conditions as TJ. Effects of impairments in the test signal due to the test system are removed from
-12
, is measured at the 50% signal level using test pattern 2 defined in IEEE P802.3ae clause 52.9.1, or equivalent,
DI pp
= 'V
Symbol
T
V
V
'V
V
Vih
Vil
T
t
Cac
RSTL PW
C
CC
CC
DI CM
Wr
DIH
DI pp
25
33
– 'V
DI CM
DIL
where 'V
= (V
Min
0
2.375
3.135
2.5
175
0.35
30
2
GND
40
10
0.5
Dinp
+ V
DIH
Dinn
= High State Differential Data Input Voltage and 'V
)/2.
Typ
40
2.5
3.3
100
0.1
Max
70
2.625
3.465
10
1400
V
48
15
30
Vcc33
0.8
400
100
50
CC
33-0.35
Units
°C
V
V
GBd
mVpp
V
ps
ps
ps
V
V
kHz
mS
Ps
mVpp
Ohms
PF
m
Reference
1
Figures 12, 13
Figures 12, 13
2
3, Figure 14
4
5
6
Figure 17
Figure 19
7, 500 Hz to
2.7 GHz
Figure 3
8, Figure 3
9
DIL
= Low State