afbr-820bz Avago Technologies, afbr-820bz Datasheet - Page 16

• Manufacturer Part Number: afbr-820bz
• Description: Twelve-channel Transmitter And Receiver Pluggable, Parallel-fiber-optic Modules
• Manufacturer: Avago Technologies

Receiver Module Contact Assignment and Signal Description
Figure 10. Host Board Pattern for Receiver Connector – Top View
16
PIN name
Adr[2:0]
Dout[11:0]p
Dout[11:0]n
DNC
GND
IntL
ResetL
SDA
SCL
Vcc25
Vcc33
Case
Common
ResetL GND Dout2p GND Dout5n GND Dout7n GND Dout9p GND
Vcc25 Vcc33 Vcc33
Adr2
Adr1
GND Dout0p GND Dout3p GND Dout6n GND Dout10n GND
GND Dout0n GND Dout3n GND Dout6p GND Dout10p GND
DNC
DNC
GND
Adr0
10
GND
GND Dout1p GND Dout4p GND Dout8n GND Dout11n GND
GND Dout1n GND Dout4n GND Dout8p GND Dout11p GND
GND Dout2n GND Dout5p GND Dout7p GND Dout9n GND
DNC
GND
9
Functional descriptions
TWS Module Bus Address bits: Address has the form 0101hjkx where Adr2, Adr1 & Adr0
correspond to h, j & k respectively and x corresponds to the R/W command.
Receiver Data Non-inverting Output for channels 11 through 0
Receiver Data Inverting Output for channels 11 through 0
Reserved – Do Not Connect to any electrical potential on Host PCB
Signal Common: All module voltages are referenced to this potential unless otherwise
stated. Connect these pins directly to the host board signal ground plane.
Interrupt signal to Host, Asserted Low: An interrupt is generated in response to loss of input
signal or assertion of any monitor Flag. It may be programmed through the TWS interface
to generate either a pulse or static level with static mode as default. This output presents a
High-Z condition when IntL is de-asserted and requires a pull-up on the Host board. Pull-up
to the Host 3.3 V supply is recommended.
Reset signal to module, Asserted Low: When asserted the data outputs, Dout[11:0]p/n are
squelched, TWS interface commands are inhibited, and the module returns to default and
non-volatile settings. An internal pullup biases the input High if the input is open.
TWS interface data signal: Pull-up with a 2.0 kΩ to 8.0 k: resistor to the Host 3.3 V supply is
recommended.
TWS interface clock signal: Pull-up with a 2.0 kΩ to 8.0 k: resistor to the Host 3.3 V supply is
recommended.
2.5V Power supply, External common connection of pins required – not common internally
3.3 V Power supply, External common connection of pins required – not common internally
Not accessible in connector. Case common incorporates exposed conductive surfaces
including threaded bosses and is electrically isolated from signal common, i.e. GND. Connect
as appropriate for EMI shield integrity. See EMI clip and bezel cutout recommendation.
GND
GND
GND
8
GND
DNC
DNC
DNC
7
Optical Connector Side
GND
GND
DNC
DNC
6
GND
DNC
DNC
DNC
5
GND
GND
DNC
DNC
4
Vcc33 Vcc33 Vcc25
GND
DNC
GND
3
GND
GND
GND
2
DNC
GND
SDA
SCL
IntL
1
G
K
H
F
E
D
C
B
A
J
I/O
I
O
O
O
I
I/O
I
P
P
Type
3.3V LVTTL
CML
CML
3.3V LVTTL,
high-Z or
driven to 0
level
3.3V LVTTL
3.3V LVTTL/
Open-Drain
3.3V LVTTL