CYUSB3011-BZXC CYPRESS [Cypress Semiconductor], CYUSB3011-BZXC Datasheet
CYUSB3011-BZXC
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CYUSB3011-BZXC Summary of contents
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Features ■ Universal serial bus (USB) integration ❐ USB 3.0 and USB 2.0 peripherals compliant with USB 3.0 specification 1.0 ❐ 5-Gbps USB 3.0 PHY compliant with PIPE 3.0 ❐ High-speed On-The-Go (HS-OTG) host and peripheral compliant with OTG Supplement ...
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Contents Functional Overview .......................................................... 3 Application Examples .................................................... 3 USB Interface ...................................................................... 4 OTG............................................................................... 4 ReNumeration ............................................................... 5 EZ-Dtect ........................................................................ 5 VBUS Overvoltage Protection ....................................... 5 Carkit UART Mode ........................................................ 5 GPIF II .................................................................................. 6 CPU ...................................................................................... 6 JTAG Interface ...
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Functional Overview Cypress’s EZ-USB FX3 is the next-generation USB 3.0 peripheral controller, providing integrated and flexible features. FX3 has a fully configurable, parallel, general programmable interface called GPIF II, which can connect to any processor, ASIC, or FPGA. GPIF II ...
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External Slave Device (Example: Image sensor clock input may be provided on the CLKIN pin instead of a crystal input USB Interface FX3 complies with the following specifications and supports the following features: ■ Supports USB peripheral functionality ...
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OTG Connectivity In OTG mode, FX3 can be configured dual-role device. It can connect to the following: ■ ACA device ■ Targeted USB peripheral ■ SRP-capable USB peripheral ■ HNP-capable USB peripheral ■ OTG ...
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Figure 5. Carkit UART Pass-through Block Diagram Carkit UART Pass-through ( ) Interface on GPIF II Carkit UART Pass-through Interface on GPIOs GPIF II The high-performance GPIF II interface enables functionality similar to, but more advanced than, FX2LP's GPIF and ...
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JTAG Interface FX3’s JTAG interface has a standard five-pin interface to connect to a JTAG debugger in order to debug firmware through the CPU-core's on-chip-debug circuitry. Industry-standard debugging tools for the ARM926EJ-S core can be used for the FX3 application ...
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Boot Options FX3 can load boot images from various sources, selected by the configuration of the PMODE pins. Following are the FX3 boot options: ■ Boot from USB 2 ■ Boot from I C ■ Boot from SPI (SPI devices ...
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Table 4. FX3 Input Clock Specifications Parameter Phase noise 100-Hz offset 1- kHz offset 10-kHz offset 100-kHz offset 1-MHz offset Maximum frequency deviation Duty cycle Overshoot Undershoot Rise time/fall time 32-kHz Watchdog Timer Clock Input FX3 includes a watchdog timer. ...
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Table 6. Entry and Exit Methods for Low-Power Modes Low-Power Mode Characteristics ■ Suspend Mode with The power consumption in this mode does USB 3.0 PHY not exceed ISB Enabled (L1) ■ USB 3.0 PHY is enabled and is in ...
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Table 6. Entry and Exit Methods for Low-Power Modes (continued) Low-Power Mode Characteristics ■ Standby Mode (L3) The power consumption in this mode does not exceed ISB3 ■ All configuration register settings and program/data RAM contents are preserved. However, data ...
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Configuration Options Configuration options are available for specific usage models. Contact Cypress Applications or Marketing for details. Digital I/Os FX3 has internal firmware-controlled pull-up or pull-down resistors on all digital I/O pins. An internal 50-kΩ resistor pulls the pins high, ...
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Pin Description Table 7. CYUSB3012 and CYUSB3014 Pin List (GPIF II with 32-bit Data Bus Width) Pin I/O F10 VIO1 I/O F9 VIO1 I/O F7 VIO1 I/O G10 VIO1 I/O G9 VIO1 I/O F8 VIO1 I/O H10 VIO1 I/O H9 ...
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Table 7. CYUSB3012 and CYUSB3014 Pin List (GPIF II with 32-bit Data Bus Width) (continued) Pin I/O H3 VIO2 I/O GPIO[40] F4 VIO2 I/O GPIO[41] G2 VIO2 I/O GPIO[42] G3 VIO2 I/O GPIO[43] F3 VIO2 I/O GPIO[44] F2 VIO2 I/O ...
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Table 7. CYUSB3012 and CYUSB3014 Pin List (GPIF II with 32-bit Data Bus Width) (continued) Pin I/O E7 VIO5 I C10 VIO5 O B11 VIO5 I E8 VIO5 I F6 VIO5 I D11 VIO5 O E10 PWR B10 PWR A1 ...
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... Table 8. CYUSB3011 and CYUSB3013 Pin List (GPIF II with 16-bit Data Bus Width) Pin I/O F10 VIO1 I/O F9 VIO1 I/O F7 VIO1 I/O G10 VIO1 I/O G9 VIO1 I/O F8 VIO1 I/O H10 VIO1 I/O H9 VIO1 I/O J10 VIO1 I/O J9 VIO1 I/O K11 VIO1 I/O L10 VIO1 I/O K10 VIO1 I/O K9 VIO1 I/O J8 VIO1 I/O G8 VIO1 I/O J6 VIO1 I/O K8 VIO1 I/O K7 VIO1 I/O J7 VIO1 I/O H7 VIO1 ...
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... Table 8. CYUSB3011 and CYUSB3013 Pin List (GPIF II with 16-bit Data Bus Width) (continued) Pin I/O H3 VIO2 I/O F4 VIO2 I/O G2 VIO2 I/O G3 VIO2 I/O F3 VIO2 I/O F2 VIO2 I/O F5 VIO3 I/O E1 VIO3 I/O E5 VIO3 I/O E4 VIO3 I/O D1 VIO3 I/O D2 VIO3 I/O D3 VIO3 I/O D4 VIO4 I/O C1 VIO4 I/O C2 VIO4 I/O D5 VIO4 I/O C4 VIO4 I/O C9 VBUS/ I VBATT A3 U3RXVDDQ I A4 U3RXVDDQ I A6 U3TXVDDQ O A5 U3TXVDDQ ...
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... Table 8. CYUSB3011 and CYUSB3013 Pin List (GPIF II with 16-bit Data Bus Width) (continued) Pin I/O E8 VIO5 I F6 VIO5 I D11 VIO5 O E10 PWR B10 PWR A1 PWR E11 PWR D8 PWR H11 PWR E2 PWR L9 PWR G1 PWR F1 PWR G11 PWR E3 PWR L1 PWR B1 PWR L6 PWR B6 PWR B5 PWR ...
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Absolute Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. Storage temperature............................... ...... –65 °C to +150 °C Ambient temperature with power supplied (Industrial).................... ... ...... –40 °C to +85 °C Supply voltage to ground potential ...
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Table 9. DC Specifications (continued) Parameter Description V Output HIGH voltage OH V Output LOW voltage OL I Input leakage current for all pins except IX SSTXP/SSXM/SSRXP/SSRXM I Output High-Z leakage current for all OZ pins except SSTXP/ SSXM/ SSRXP/SSRXM ...
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AC Timing Parameters GPIF II Timing tLZ - D Q [31: TL(IN Table 10. GPIF II Timing Parameters in Synchronous Mode Parameter Frequency Interface clock frequency tCLK ...
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DATA/ ADDR tCTLassert_DQlatch CTL# (I/P , ALE/ DLE) DATA OUT CTL# (I/P, non ALE/ DLE tCTLalpha ALPHA O/P tCTLbeta BETA O/P tCTLassert tCTL# (O/ integer >= 0 tDST DATA/ ADDR CTL# I/P (non DLE/ALE) Figure 10. ...
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Table 11. GPIF II Timing in Asynchronous Mode Note The following parameters assume one state transition Parameter tDS Data In to DLE setup time. Valid in DDR async mode. tDH Data In to DLE hold time. Valid in DDR async ...
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Slave FIFO Interface Synchronous Slave FIFO Sequence Description ■ FIFO address is stable and SLCS is asserted ■ SLOE is asserted. SLOE is an output-enable only, whose sole function is to drive the data bus. ■ SLRD is asserted ■ ...
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Synchronous Slave FIFO Write Sequence Description ■ FIFO address is stable and the signal SLCS# is asserted ■ External master or peripheral outputs the data to the data bus ■ SLWR# is asserted ■ While the SLWR# is asserted, data ...
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Table 12. Synchronous Slave FIFO Parameters Parameter FREQ Interface clock frequency tCYC Clock period tCH Clock high time tCL Clock low time tRDS SLRD# to CLK setup time tRDH SLRD# to CLK hold time tWRS SLWR# to CLK setup time ...
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SLCS t AS FIFO ADDR SLRD SLOE t FLG FLAGA dedicated thread Flag for An (1=Not empty 0 = Empty) FLAGB dedicated thread Flag for Am (1=Not empty 0 = Empty Data Out High-Z SLWR (HIGH) ...
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Asynchronous Write Cycle Timing SLCS t AS FIFO ADDR SLWR t FLG FLAGA dedicated thread Flag for An (1=Not Full 0 = Full) FLAGB dedicated thread Flag for Am (1=Not Full 0 = Full) High-Z DATA In PKTEND SLOE (HIGH) ...
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Table 13. Asynchronous Slave FIFO Parameters Parameter tRDI SLRD# low tRDh SLRD# high tAS Address to SLRD#/SLWR# setup time tAH SLRD#/SLWR#/PKTEND to address hold time tRFLG SLRD# to FLAGS output propagation delay tFLG ADDR to FLAGS output propagation delay tRDO ...
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Table 14 Timing Parameters Parameter fSCL SCL clock frequency tHD:STA Hold time START condition tLOW LOW period of the SCL tHIGH HIGH period of the SCL tSU:STA Setup time for a repeated START condition tHD:DAT Data ...
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Table 14 Timing Parameters (continued) Parameter tr Rise time of both SDA and SCL signals tf Fall time of both SDA and SCL signals tSU:STO Setup time for STOP condition tBUF Bus-free time between a STOP ...
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SPI Timing Specification SSN (output) SCK (CPOL=0, Output) SCK (CPOL=1, Output) MISO (input) MOSI (output) SSN (output) SCK (CPOL=0, Output) SCK (CPOL=1, Output) MISO (input) MOSI (output) Document Number: 001-52136 Rev. *L Figure 17. SPI Timing t sck t lead ...
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Table 16. SPI Timing Parameters Parameter Description fop Operating frequency tsck Cycle time twsck Clock high/low time tlead SSN-SCK lead time tlag Enable lag time trf Rise/fall time tsdd Output SSN to valid data delay time tdv Output data ...
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VDD ( core ) xVDDQ XTALIN/ CLKIN Mandatory Reset Pulse RESET # tRPW Standby/ Suspend Source Document Number: 001-52136 Rev. *L Figure 18. Reset Sequence tRR tRh Hard Reset Standby/Suspend source Is asserted (MAIN_POWER_EN/ MAIN_CLK_EN bit is set) CYUSB301X XTALIN/ ...
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Package Diagram Document Number: 001-52136 Rev. *L Figure 19. 121-Ball FBGA 10 × 10 × 1.2 Diagram CYUSB301X 001-54471 *C Page ...
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... Ordering Information Table 18. Ordering Information Ordering Code CYUSB3011-BZXC CYUSB3012-BZXC CYUSB3013-BZXC CYUSB3014-BZXC CYUSB3014-BZXI Ordering Code Definition 3 XXX BZX I/C CY USB Document Number: 001-52136 Rev. *L SRAM (kB) GPIF II Data Bus Width 256 16-bit 256 32-bit 512 16-bit 512 32-bit 512 32-bit Temperature range : Industrial/Commercial Package type: BGA Marketing Part Number Base part number for USB 3 ...
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Acronyms Acronym Description DMA direct memory access HNP host negotiation protocol MMC multimedia card MTP media transfer protocol PLL phase locked loop PMIC power management IC SD secure digital SD secure digital SDIO secure digital input / output SLC single-level ...
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... Changed title to EZ-USB™ FX3: SuperSpeed USB Controller 12/08/09 Added data sheet to the USB 3.0 EROS spec 001-51884. No technical updates. 11/08/2010 Changed status from Advance to Preliminary Changed part number from CYUSB3011 to CYUSB3014 Added the following sections: Power, System-level ESD, Absolute Maximum Reset Sequence, ...
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... Corrected typo in the block diagram. 08/16/2012 Changed part number to CYUSB301X. Added 256 KB range for embedded SRAM. Updated Functional Overview, Other Interfaces, and Clocking sections. Added Pin List for CYUSB3011 and CYUSB3013 parts. Updated Ordering Information with new part numbers. CYUSB301X Description of Change and I ...
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