CYUSB3011-BZXC CYPRESS [Cypress Semiconductor], CYUSB3011-BZXC Datasheet - Page 23

• Manufacturer Part Number: CYUSB3011-BZXC
• Manufacturer: CYPRESS [Cypress Semiconductor]

Table 11. GPIF II Timing in Asynchronous Mode
Note The following parameters assume one state transition
Document Number: 001-52136 Rev. *L
Note
tDS
tDH
tAS
tAH
tCTLassert
tCTLdeassert
tCTLassert_DQassert
tCTLdeassert_DQassert
tCTLassert_DQdeassert
tCTLdeassert_DQdeassert
tCTLassert_DQlatch
tCTLdeassert_DQlatch
tCTLassert_DQlatchDDR
tCTLdeassert_DQlatchDDR
tAA
tDO
tOELZ
tOEHZ
tCLZ
tCHZ
tCTLalpha
tCTLbeta
tDST
tDHT
5. All parameters guaranteed by design and validated through characterization.
Parameter
Data In to DLE setup time. Valid in DDR async mode.
Data In to DLE hold time. Valid in DDR async mode.
Address In to ALE setup time
Address In to ALE hold time
CTL I/O asserted width for CTRL inputs without DQ input
association and for outputs.
CTL I/O deasserted width for CTRL inputs without DQ
input association and for outputs.
CTL asserted pulse width for CTL inputs that signify DQ
inputs valid at the asserting edge but do not employ
in-built latches (ALE/DLE) for those DQ inputs.
CTL deasserted pulse width for CTL inputs that signify DQ
input valid at the asserting edge but do not employ in-built
latches (ALE/DLE) for those DQ inputs.
CTL asserted pulse width for CTL inputs that signify DQ
inputs valid at the deasserting edge but do not employ
in-built latches (ALE/DLE) for those DQ inputs.
CTL deasserted pulse width for CTL inputs that signify DQ
inputs valid at the deasserting edge but do not employ
in-built latches (ALE/DLE) for those DQ inputs.
CTL asserted pulse width for CTL inputs that employ
in-built latches (ALE/DLE) to latch the DQ inputs. In this
non-DDR case, in-built latches are always close at the
deasserting edge.
CTL deasserted pulse width for CTL inputs that employ
in-built latches (ALE/DLE) to latch the DQ inputs. In this
non-DDR case, in-built latches always close at the
deasserting edge.
CTL asserted pulse width for CTL inputs that employ
in-built latches (DLE) to latch the DQ inputs in DDR mode.
CTL deasserted pulse width for CTL inputs that employ
in-built latches (DLE) to latch the DQ inputs in DDR mode.
DQ/CTL input to DQ output time when DQ change or CTL
change needs to be detected and affects internal updates
of input and output DQ lines.
CTL to data out when the CTL change merely enables the
output flop update whose data was already established.
CTL designated as OE to low-Z. Time when external
devices should stop driving data.
CTL designated as OE to high-Z
CTL (non-OE) to low-Z. Time when external devices
should stop driving data.
CTL (non-OE) to high-Z
CTL to alpha change at output
CTL to beta change at output
Addr/data setup when DLE/ALE not used
Addr/data hold when DLE/ALE not used
[5]
Description
Min
2.3
2.3
20
20
10
10
10
30
20
2
2
7
7
7
7
7
–
–
0
8
0
–
–
2
Max
CYUSB301X
30
25
30
25
30
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
8
–
–
–
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Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns