CYUSB3011-BZXC CYPRESS [Cypress Semiconductor], CYUSB3011-BZXC Datasheet - Page 9

• Manufacturer Part Number: CYUSB3011-BZXC
• Manufacturer: CYPRESS [Cypress Semiconductor]

Table 4. FX3 Input Clock Specifications
32-kHz Watchdog Timer Clock Input
FX3 includes a watchdog timer. The watchdog timer can be used
to interrupt the ARM926EJ-S core, automatically wake up the
FX3 in Standby mode, and reset the ARM926EJ-S core. The
watchdog timer runs a 32-kHz clock, which may be optionally
supplied from an external source on a dedicated FX3 pin.
The firmware can disable the watchdog timer.
Requirements for the optional 32-kHz clock input are listed in
Table
Table 5. 32-kHz Clock Input Requirements
Power
FX3 has the following power supply domains:
■
Document Number: 001-52136 Rev. *L
Phase noise
Maximum frequency deviation
Duty cycle
Overshoot
Undershoot
Rise time/fall time
Duty cycle
Frequency deviation
Rise time/fall time
IO_VDDQ : This is a group of independent supply domains for
digital I/Os. The voltage level on these supplies is 1.8 V to 3.3 V.
FX3 provides six independent supply domains for digital I/Os
listed as follows (see
domain signals):
❐
❐
❐
❐
❐
VIO1: GPIF II I/O
VIO2: IO2
VIO3: IO3
VIO4: UART-/SPI/I
VIO5: I
5.
Parameter
2
Parameter
C and JTAG (supports 1.2 V to 3.3 V)
2
Table 7
S
for details on each of the power
Min
40
–
–
100-Hz offset
1- kHz offset
10-kHz offset
100-kHz offset
1-MHz offset
±200
Max
200
60
Description
Units
ppm
ns
%
■
Power Modes
FX3 supports the following power modes:
■
■
❐
❐
VBATT/VBUS : This is the 3.2-V to 6-V battery power supply
for the USB I/O and analog circuits. This supply powers the
USB transceiver through FX3's internal voltage regulator.
VBATT is internally regulated to 3.3 V.
Normal mode: This is the full-functional operating mode. The
internal CPU clock and the internal PLLs are enabled in this
mode.
❐
❐
Low-power modes (see
❐
❐
❐
❐
CVDDQ: Clock
V
supply-voltage level is 1.2 V. This supplies the core logic
circuits. The same supply must also be used for the following:
• AVDD: This is the 1.2-V supply for the PLL, crystal oscilla-
• U3TXVDDQ/U3RXVDDQ : These are the 1.2-V supply volt-
Normal operating power consumption does not exceed the
sum of I
current consumption specifications).
The I/O power supplies VIO2, VIO3, VIO4, and VIO5 can be
turned off when the corresponding interface is not in use.
VIO1 cannot be turned off at any time if the GPIF II interface
is used in the application.
Suspend mode with USB 3.0 PHY enabled (L1)
Suspend mode with USB 3.0 PHY disabled (L2)
Standby mode (L3)
Core power-down mode (L4)
DD
tor, and other core analog circuits
ages for the USB 3.0 interface.
: This is the supply voltage for the logic core. The nominal
CC
Min
30
–
–
–
–
–
–
–
–
–
Core max and I
Specification
Table 6
CC
–104
–120
–128
–130
Max
–75
150
70
–3
3
3
USB max (see
on page 10):
CYUSB301X
Page 9 of 40
Table 7
Units
ppm
dB
dB
dB
dB
dB
ns
%
%
%
for