CYUSB3011-BZXC CYPRESS [Cypress Semiconductor], CYUSB3011-BZXC Datasheet - Page 12

• Manufacturer Part Number: CYUSB3011-BZXC
• Manufacturer: CYPRESS [Cypress Semiconductor]

Configuration Options
Configuration options are available for specific usage models.
Contact Cypress Applications or Marketing for details.
Digital I/Os
FX3 has internal firmware-controlled pull-up or pull-down
resistors on all digital I/O pins. An internal 50-kΩ resistor pulls
the pins high, while an internal 10-kΩ resistor pulls the pins low
to prevent them from floating. The I/O pins may have the
following states:
■
■
■
■
■
All unused I/Os should be pulled high by using the internal
pull-up resistors. All unused outputs should be left floating. All
I/Os can be driven at full-strength, three-quarter strength,
half-strength, or quarter-strength. These drive strengths are
configured separately for each interface.
GPIOs
EZ-USB enables a flexible pin configuration both on the GPIF II
and the serial peripheral interfaces. Any unused control pins
(except CTL[15]) on the GPIF II interface can be used as GPIOs.
Document Number: 001-52136 Rev. *L
Tristated (High-Z)
Weak pull-up (via internal 50 kΩ)
Pull-down (via internal 10 kΩ)
Hold (I/O hold its value) when in low-power modes
The JTAG TDI, TMC, and TRST# signals have fixed 50-kΩ
internal pull-ups, and the TCK signal has a fixed 10-kΩ
pull-down resistor.
A
B
C
D
E
F
G
H
K
J
L
GPIO[38]
U3VSSQ
GPIO[54]
GPIO[50]
GPIO[47]
GPIO[35]
VIO4
VIO2
VDD
VSS
VSS
1
U3RXVDDQ
GPIO[42]
GPIO[39]
GPIO[36]
GPIO[33]
GPIO[55]
GPIO[45]
FSLC[0]
GPIO[51 ]
VSS
VSS
2
GPIO[44]
GPIO[43]
GPIO[40]
R_USB3
GPIO[52]
GPIO[37]
SSRXM
VIO3
VDD
VSS
VSS
3
Figure 7. FX3 Ball Map (Top View)
GPIO[49]
GPIO[30]
GPIO[34]
GPIO[32]
GPIO[57]
GPIO[53]
GPIO[41 ]
GPIO[31 ]
FSLC[1 ]
SSRXP
VSS
4
U3TXVDDQ
GPIO[48]
GPIO[46]
GPIO[29]
GPIO[28]
GPIO[56]
GPIO[25]
GPIO[27]
RESET#
SSTXP
VDD
5
CLKIN_32
Similarly, any unused pins on the serial peripheral interfaces may
be configured as GPIOs. See the on page 16 for pin configu-
ration options.
All GPIF II and GPIO pins support an external load of up to 16 pF
for every pin.
EMI
FX3 meets EMI requirements outlined by FCC 15B (USA) and
EN55022 (Europe) for consumer electronics. FX3 can tolerate
reasonable EMI, conducted by the aggressor, outlined by these
specifications and continue to function as expected.
System-level ESD
FX3 has built-in ESD protection on the D+, D–, and GND pins on
the USB interface. The ESD protection levels provided on these
ports are:
■
■
■
This protection ensures the device continues to function after
ESD events up to the levels stated in this section.
The SSRX+, SSRX–, SSTX+, and SSTX– pins only have up to
±2.2-KV HBM internal ESD protection.
GPIO[22]
GPIO[26]
GPIO[23]
GPIO[1 6]
CVDDQ
FSLC[2]
SSTXM
XTALIN
TCK
VSS
±2.2-KV human body model (HBM) based on JESD22-A114
Specification
±6-KV contact discharge and ±8-KV air gap discharge based
on IEC61000-4-2 level 3A
± 8-KV Contact Discharge and ±15-KV Air Gap Discharge
based on IEC61000-4-2 level 4C.
6
XTALOUT
GPIO[20]
GPIO[21 ]
GPIO[1 9]
GPIO[1 8]
AV DD
GPIO[2]
AV SS
CLKIN
VDD
TDI
7
GPIO[24]
R_USB2
GPIO[1 5]
GPIO[1 4]
GPIO[1 7]
GPIO[5]
V SS
TMS
INT#
VSS
VSS
8
I2C_GPIO[58] I2C_GPIO[59]
GPIO[1 3]
OTG_ID
GPIO[4]
GPIO[7]
GPIO[9]
GPIO[1 ]
VDD
VIO1
VSS
DP
9
V BATT
GPIO[1 2]
GPIO[1 1 ]
GPIO[0]
GPIO[3]
GPIO[6]
GPIO[8]
CYUSB301X
V DD
TDO
DM
1 0
Page 12 of 40
GPIO[1 0]
V BUS
TRST#
O[60]
VIO5
VDD
VDD
VSS
VIO1
VSS
NC
1 1