CYUSB3011-BZXC CYPRESS [Cypress Semiconductor], CYUSB3011-BZXC Datasheet - Page 26

• Manufacturer Part Number: CYUSB3011-BZXC
• Manufacturer: CYPRESS [Cypress Semiconductor]

Table 12. Synchronous Slave FIFO Parameters
.
Asynchronous Slave FIFO Read Sequence
Description
■
■
■
■
■
Document Number: 001-52136 Rev. *L
Note
FREQ
tCYC
tCH
tCL
tRDS
tRDH
tWRS
tWRH
tCO
tDS
tDH
tAS
tAH
tOELZ
tCFLG
tOEZ
tPES
tPEH
tCDH
Note Three-cycle latency from ADDR to DATA/FLAGS
6. All parameters guaranteed by design and validated through characterization.
FIFO address is stable and the SLCS# signal is asserted.
SLOE# is asserted. This results in driving the data bus.
SLRD # is asserted.
Data from the FIFO is driven after assertion of SLRD#. This
data is valid after a propagation delay of tRDO from the falling
edge of SLRD#.
FIFO pointer is incremented on deassertion of SLRD#
Parameter
Interface clock frequency
Clock period
Clock high time
Clock low time
SLRD# to CLK setup time
SLRD# to CLK hold time
SLWR# to CLK setup time
SLWR# to CLK hold time
Clock to valid data
Data input setup time
CLK to data input hold
Address to CLK setup time
CLK to address hold time
SLOE# to data low-Z
CLK to flag output propagation delay
SLOE# deassert to Data Hi Z
PKTEND# to CLK setup
CLK to PKTEND# hold
CLK to data output hold
[6]
Description
In
data to appear on the data bus during the read cycle, SLOE#
must be in an asserted state. SLRD# and SLOE# can also be
tied.
The same sequence of events is also shown for a burst read.
Note In the burst read mode, during SLOE# assertion, the data
bus is in a driven state (data is driven from a previously
addressed FIFO). After assertion of SLRD# data from the FIFO
is driven on the data bus (SLOE# must also be asserted). The
FIFO pointer is incremented after deassertion of SLRD#.
Figure
13, data N is the first valid data read from the FIFO. For
Min
0.5
0.5
0.5
0.5
0.5
10
–
4
4
2
2
–
2
2
0
–
–
2
2
CYUSB301X
Max
100
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–
–
–
–
–
–
–
8
–
–
–
–
–
8
8
–
–
–
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns