CYUSB3011-BZXC CYPRESS [Cypress Semiconductor], CYUSB3011-BZXC Datasheet - Page 27

• Manufacturer Part Number: CYUSB3011-BZXC
• Manufacturer: CYPRESS [Cypress Semiconductor]

Asynchronous Slave FIFO Write Sequence
Description
■
■
■
■
■
The same sequence of events is shown for a burst write.
Note that in the burst write mode, after SLWR# deassertion, the
data is written to the FIFO, and then the FIFO pointer is incre-
mented.
Document Number: 001-52136 Rev. *L
dedicated thread Flag for An
(1=Not empty 0 = Empty)
FIFO address is driven and SLCS# is asserted
SLWR# is asserted. SLCS# must be asserted with SLWR# or
before SLWR# is asserted
Data must be present on the tWRS bus before the deasserting
edge of SLWR#
Deassertion of SLWR# causes the data to be written from the
data bus to the FIFO, and then the FIFO pointer is incremented
The FIFO flag is updated after the tWFLG from the deasserting
edge of SLWR.
dedicated thread Flag for Am
(1=Not empty 0 = Empty)
FIFO ADDR
Data Out
FLAGA
SLRD
SLCS
SLOE
FLAGB
SLWR
(HIGH)
High-Z
t
FLG
t
t
LZ
AS
t
OE
Figure 13. Asynchronous Slave FIFO Read Mode
t
t
RDO
RDl
An
D
N
(An)
t
RDh
t
OH
t
AH
t
RFLG
Short Packet : A short packet can be committed to the USB host
by using the PKTEND#. The external device or processor should
be designed to assert the PKTEND# along with the last word of
data and SLWR# pulse corresponding to the last word. The
FIFOADDR lines must be held constant during the PKTEND#
assertion.
Zero-Length Packet : The external device or processor can
signal a zero-length packet (ZLP) to FX3 simply by asserting
PKTEND#, without asserting SLWR#. SLCS# and the address
must be driven as shown in
FLAG Usage : The FLAG signals are monitored by the external
processor for flow control. FLAG signals are FX3 outputs that
can be configured to show empty, full, and partial status for a
dedicated address or the current address.
Am
t
OE
D
N
t
(An)
RDO
D
N
(Am)
t
RDO
Figure 14
D
N+1
(Am)
on page 28.
D
N+2
(Am)
CYUSB301X
Page 27 of 40
t
OH