CYUSB3011-BZXC CYPRESS [Cypress Semiconductor], CYUSB3011-BZXC Datasheet - Page 25

• Manufacturer Part Number: CYUSB3011-BZXC
• Manufacturer: CYPRESS [Cypress Semiconductor]

Synchronous Slave FIFO Write Sequence Description
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■
■
■
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The same sequence of events is also shown for burst write
Note For the burst mode, SLWR# and SLCS# are asserted for
the entire duration, during which all the required data values are
written. In this burst write mode, after the SLWR# is asserted, the
data on the FIFO data bus is written to the FIFO on every rising
Document Number: 001-52136 Rev. *L
FIFO address is stable and the signal SLCS# is asserted
External master or peripheral outputs the data to the data bus
SLWR# is asserted
While the SLWR# is asserted, data is written to the FIFO and
on the rising edge of the PCLK, the FIFO pointer is incremented
The FIFO flag is updated after a delay of t
edge of the clock
dedicated thread FLAG for An
(1 = Not Full 0= Full)
current thread FLAG for Am
(1 = Not Full 0= Full)
FIFO ADDR
FLAGB
FLAGA
PKTEND
SLCS
Data IN
SLWR
SLOE
(HIGH)
PCLK
Figure 12. Synchronous Slave FIFO Write Mode
Synchronous Write Cycle Timing
WFLG
High-Z
dedicated thread FLAG for An
(1 = Not Full 0= Full)
current thread FLAG for Am
(1 = Not Full 0= Full)
t
AS
from the rising
t
AH
t
CH
FIFO ADDR
t
t
WRS
CYC
FLAGB
Synchronous ZLP Write Cycle Timing
FLAGA
PKTEND
D
t
t
SLCS
Data IN
An
DS
SLWR
(HIGH)
SLOE
(HIGH)
CL
N
(An)
PCLK
t
3 cycle latency from SLWR# to FLAG
DH
t
WRH
High-Z
t
PES
t
AS
t
t
PEH
t
AH
CH
edge of PCLK. The FIFO pointer is updated on each rising edge
of PCLK.
Short Packet : A short packet can be committed to the USB host
by using the PKTEND#. The external device or processor should
be designed to assert the PKTEND# along with the last word of
data and SLWR# pulse corresponding to the last word. The
FIFOADDR lines must be held constant during the PKTEND#
assertion.
Zero-Length Packet : The external device or processor can
signal a Zero-Length Packet (ZLP) to FX3 simply by asserting
PKTEND#, without asserting SLWR#. SLCS# and address must
be driven as shown in
FLAG Usage : The FLAG signals are monitored for flow control
by the external processor. FLAG signals are outputs from FX3
that may be configured to show empty, full, or partial status for a
dedicated thread or the current thread that is addressed.
t
CYC
t
An
CL
t
DS
D
N
(Am)
t
t
CFLG
DH
Am
D
N+1
(Am) D
t
N+2
PES
t
(Am)
CFLG
3 cycle latency from SLWR # to FLAG
t
PEH
t
DH
Figure 12
on page 25.
t
CFLG
CYUSB301X
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