IDT72V51556L7-5BB8 IDT, Integrated Device Technology Inc, IDT72V51556L7-5BB8 Datasheet - Page 18

• Manufacturer Part Number: IDT72V51556L7-5BB8
• Description: IC FLOW CTRL MULTI QUEUE 256-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72V51556L7-5BB8

• Configuration: Dual
• Density: 2Mb
• Access Time (max): 4ns
• Word Size: 36b
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: BGA
• Clock Freq (max): 133MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.15V
• Operating Supply Voltage (max): 3.6V
• Supply Current: 100mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 256
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V51556L7-5BB8

TABLE 1 — WRITE ADDRESS BUS, WRADD[7:0]
queue device is used, the completion of device programming is signaled by the
SENO output of a device going from HIGH to LOW. Note, that SENI must be
held LOW when a device is setup for default programming mode.
the first device in a chain can be held LOW. The SENO of a device should
connect to the SENI of the next device in the chain. The SENO of the final device
is used to indicate that default programming of all devices is complete. When the
final SENO goes LOW normal operations may begin. Again, all devices will be
programmed with their maximum number of queues and the memory divided
equally between them. Please refer to Figure 8, Default Programming.
READING AND WRITING TO THE IDT MULTI-QUEUE
FLOW CONTROL MANAGER
configured in two distinct modes, namely Standard Mode and Packet Mode.
STANDARD MODE OPERATION (PKT = LOW on Master Reset)
WRITE QUEUE SELECTION AND WRITE OPERATION
(STANDARD MODE)
configured up to a maximum of 32 queues into which data can be written via
a common write port using the data inputs (Din), write clock (WCLK) and write
enable (WEN). The queue to be written is selected by the address present
on the write address bus (WRADD) during a rising edge on WCLK while write
address enable (WADEN) is HIGH. The state of WEN does not impact the
IDT72V51546/72V51556 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
When multi-queue devices are connected in expansion mode, the SENI of
The IDT72V51546/72V51556 multi-queue flow-control devices can be
The IDT72V51546/72V51556 multi-queue flow-control devices can be
PAFn Quadrant
Write Queue
Operation WCLK WADEN
Select
Select
1
0
Quadrant
Address
00
01
10
11
FSTR
18
0
1
queue selection. The queue selection is requires 2 WCLK cycles. All subse-
quent data writes will be to this queue until another queue is selected.
device as opposed to Packet Mode where complete packets may be written.
The write port is designed such that 100% bus utilization can be obtained. This
means that data can be written into the device on every WCLK rising edge
including the cycle that a new queue is being addressed.
(see Figure 9, Write Queue Select, Write Operation and Full flag Operation).
WADEN goes high signaling a change of queue (clock cycle “A”). The address
on WRADD at that time determines the next queue. Data presented during that
cycle (“A”) and the next cycle (“B”), will be written to the active (old) queue,
provided WEN is active LOW. If WEN is HIGH (inactive) for these two clock
cycles, data will not be written in to the previous queue. The write port discrete
full flag will update to show the full status of the newly selected queue (Q
this last cycle’s rising edge (“B”). Data present on the data input bus (Din), can
be written into the newly selected queue (Q
the second cycle (“C”) following a change of queue, provided WEN is LOW
and the new queue is not full. If the newly selected queue is full at the point of
its selection, any writes to that queue will be prevented. Data cannot be written
into a full queue.
Operation, Figure 10, Write Operations & First Word Fall Through for timing
diagrams and Figure 11, Full Flag Timing in Expansion Mode for timing
diagrams.
Standard mode operation is defined as individual words will be written to the
Changing queues requires a minimum of 2 WCLK cycles on the write port
Refer to Figure 9, Write Queue Select, Write Operation and Full flag
Queue Status on PAFn Bus
Q0 : Q7 → PAF0 : PAF7
Q8 : Q15 → PAF0 : PAF7
Q16 : Q23 → PAF0 : PAF7
Q24 : Q31 → PAF0 : PAF7
Device Select
(Compared to
ID0,1,2)
Device Select
(Compared to
ID0,1,2)
7 6 5
7 6 5
WRADD[7:0]
Write Queue Address
(5 bits = 32 Queues)
4 3 2
4 3 2
X
X
X Quadrant
COMMERCIAL AND INDUSTRIAL
Address
1 0
1 0
5904 drw05
X
) on the rising edge of WCLK on
TEMPERATURE RANGES
X
) at