IDT72V51556L7-5BB8 IDT, Integrated Device Technology Inc, IDT72V51556L7-5BB8 Datasheet - Page 27

• Manufacturer Part Number: IDT72V51556L7-5BB8
• Description: IC FLOW CTRL MULTI QUEUE 256-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72V51556L7-5BB8

• Configuration: Dual
• Density: 2Mb
• Access Time (max): 4ns
• Word Size: 36b
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: BGA
• Clock Freq (max): 133MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.15V
• Operating Supply Voltage (max): 3.6V
• Supply Current: 100mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 256
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V51556L7-5BB8

PAFn - DIRECT BUS
mode. In direct mode the user can address the quadrant of queues they require
to be placed on to the PAFn bus. For example, consider the operation of the
PAFn bus when 26 queues have been setup. To output status of the first
quadrant, Queue[0:7] the WRADD bus is used in conjunction with the FSTR
(PAF flag strobe) input and WCLK. The address present on the 2 least
significant bits of the WRADD bus with FSTR HIGH will be selected as the
quadrant address on a rising edge of WCLK. So to address quadrant 1,
Queue[0:7] the WRADD bus should be loaded with “xxxxxx00”, the PAFn bus
will change status to show the new quadrant selected 1 WCLK cycle after
quadrant selection. PAFn[0:7] gets status of queues, Queue[0:7] respectively.
“xxxxxx01”. PAFn[0:7] gets status of queues, Queue[8:15] respectively. To
address the third quadrant, Queue[16:23], the WRADD address is “xxxxxx10”.
PAF[0:7] gets status of queues, Queue[16:23] respectively. To address the
fourth quadrant, Queue[24:31], the WRADD address is “xxxxxx11”. PAF[0:1]
gets status of queues, Queue[24:25] respectively. Remember, only 26 queues
were setup, so when quadrant 4 is selected the unused outputs PAF[2:7] will
be don't care states.
queue ‘x’ on the same cycle as a quadrant switch which will include the queue
‘x’, then there may be an extra WCLK cycle delay before that queues status
is correctly shown on the respective output of the PAFn bus. However, the
active PAF flag will show correct status at all times.
on the PAFn bus can change every WCLK cycle. Also, data present on the
input bus, Din, can be written into a queue on the same WCLK rising edge that
a quadrant is being selected, the only restriction being that a write queue
selection and PAFn quadrant selection cannot be made on the same cycle.
output on PAF[0:7] constantly.
device the PAFn busses of all devices are connected together, when switching
between quadrants of different devices the user must utilize the 3 most significant
bits of the WRADD address bus (as well as the 2 LSB’s). These 3 MSB’s
correspond to the device ID inputs, which are the static inputs, ID0, ID1 & ID2.
information. Also refer to Table 1, Write Address Bus, WRADD.
PAFn – POLLED BUS
mode. In polled mode the PAFn bus automatically cycles through the 4
quadrants within the device regardless of how many queues have been setup
in the part. Every rising edge of the WCLK causes the next quadrant to be
loaded on the PAFn bus. The device configured as the master (MAST input
tied HIGH), will take control of the PAFn after MRS goes LOW. For the whole
WCLK cycle that the first quadrant is on PAFn the FSYNC (PAFn bus sync)
output will be HIGH, for all other quadrants, this FSYNC output will be LOW.
This FSYNC output provides the user with a mark with which they can
synchronize to the PAFn bus, FSYNC is always HIGH for the WCLK cycle that
the first quadrant of a device is present on the PAFn bus.
set as the Master, MAST input tied HIGH, all other devices will have MAST
tied LOW. The master device is the first device to take control of the PAFn bus
and will place its first quadrant on the bus on the rising edge of WCLK after the
MRS input goes HIGH. For the next 3 WCLK cycles the master device will
maintain control of the PAFn bus and cycle its quadrants through it, all other
IDT72V51546/72V51556 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
If FM is LOW at master reset then the PAFn bus operates in Direct (addressed)
To address the second quadrant, Queue[8:15], the WRADD address is
Note, that if a read or write operation is occurring to a specific queue, say
Quadrants can be selected on consecutive clock cycles, that is the quadrant
If 8 or less queues are setup then queues, Queue[0:7] have their PAF status
When the multi-queue devices are connected in expansion of more than one
Please refer to Figure 27, PAF n - Direct Mode Quadrant Selection for timing
If FM is HIGH at master reset then the PAFn bus operates in Polled (looped)
When devices are connected in expansion mode, only one device will be
27
devices hold their PAFn outputs in High-Impedance. When the master device
has cycled all of its quadrants it passes a token to the next device in the chain
and that device assumes control of the PAFn bus and then cycles its quadrants
and so on, the PAFn bus control token being passed on from device to device.
This token passing is done via the FXO outputs and FXI inputs of the devices
(“PAF Expansion Out” and “PAF Expansion In”). The FXO output of the master
device connects to the FXI of the second device in the chain and the FXO of
the second connects to the FXI of the third and so on. The final device in a chain
has its FXO connected to the FXI of the first device, so that once the PAFn bus
has cycled through all quadrants of all devices, control of the PAFn will pass
to the master device again and so on. The FSYNC of each respective device
will operate independently and simply indicate when that respective device has
taken control of the bus and is placing its first quadrant on to the PAFn bus.
the FXO output of the same device. In single device mode a token is still required
to be passed into the device for accessing the PAFn bus.
PAEn/PRn FLAG BUS OPERATION
configured for up to 32 queues, each queue having its own almost empty/
packet ready status. An active queue has its flag status output to the discrete
flags, OV, PAE and PR, on the read port. Queues that are not selected for a
read operation can have their PAE/PR status monitored via the PAEn/PRn bus.
The PAEn/PRn flag bus is 8 bits wide, so that 8 queues at a time can have their
status output to the bus. If 9 or more queues are setup within a device then there
are 2 methods by which the device can share the bus between queues, "Direct"
mode and "Polled" mode depending on the state of the FM (Flag Mode) input
during a Master Reset. If 8 or less queues are setup within a device then each
will have its own dedicated output from the bus. If 8 or less queues are setup
in single device mode, it is recommended to configure the PAFn bus to polled
mode as it does not require using the write address (WRADD).
PAEn/PRn - DIRECT BUS
(addressed) mode. In direct mode the user can address the quadrant of
queues they require to be placed on to the PAEn/PRn bus. For example,
consider the operation of the PAEn/PRn bus when 26 queues have been
setup. To output status of the first quadrant, Queue[0:7] the RDADD bus is used
in conjunction with the ESTR (PAE/PR flag strobe) input and RCLK. The
address present on the 2 least significant bits of the RDADD bus with ESTR
HIGH will be selected as the quadrant address on a rising edge of RCLK. So
to address quadrant 1, Queue[0:7] the RDADD bus should be loaded with
“xxxxxx00”, the PAEn/PRn bus will change status to show the new quadrant
selected 1 RCLK cycle after quadrant selection. PAEn[0:7] gets status of
queues, Queue[0:7] respectively.
“xxxxxx01”. PAEn[0:7] gets status of queues, Queue[8:15] respectively. To
address the third quadrant, Queue[16:23], the RDADD address is “xxxxxx10”.
PAE[0:7] gets status of queues, Queue[16:23] respectively. To address the
fourth quadrant, Queue[24:31], the RDADD address is “xxxxxx11”. PAE[0:1]
gets status of queues, Queue[24:25] respectively. Remember, only 26 queues
were setup, so when quadrant 4 is selected the unused outputs PAE[2:7] will
be don't care states.
queue ‘x’ on the same cycle as a quadrant switch which will include the queue
‘x’, then there may be an extra RCLK cycle delay before that queues status
is correctly shown on the respective output of the PAEn/PRn bus.
When operating in single device mode the FXI input must be connected to
Please refer to Figure 30, PAF n Bus – Polled Mode for timing information.
The IDT72V51546/72V51556 multi-queue flow-control devices can be
If FM is LOW at master reset then the PAEn/PRn bus operates in Direct
To address the second quadrant, Queue[8:15], the RDADD address is
Note, that if a read or write operation is occurring to a specific queue, say
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES