IDT72V51556L7-5BB8 IDT, Integrated Device Technology Inc, IDT72V51556L7-5BB8 Datasheet - Page 22

• Manufacturer Part Number: IDT72V51556L7-5BB8
• Description: IC FLOW CTRL MULTI QUEUE 256-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72V51556L7-5BB8

• Configuration: Dual
• Density: 2Mb
• Access Time (max): 4ns
• Word Size: 36b
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: BGA
• Clock Freq (max): 133MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.15V
• Operating Supply Voltage (max): 3.6V
• Supply Current: 100mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 256
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V51556L7-5BB8

NULL QUEUE OPERATION (OF THE READ PORT)
utilization in standard mode. Data can be read out of the multi-queue flow-control
device on every RCLK cycle regardless of queue switches or other opera-
tions. The device architecture is such that the pipeline is constantly filled with
the next words in a selected queue to be read out, again providing 100% bus
utilization. This type of architecture does assume that the user is constantly
switching queues such that during a queue switch, the last data word required
from the previous queue will fall through the pipeline to the output.
will automatically flow through the pipeline to the output.
queue flow-control device, the 32nd queue address (xxx 11111) of the device
now is assigned as the null queue. (Note, any unused queue can be assigned
as the Null queue). During device programming the user should simply
program between 1 and 31 queues, the 32nd queue will automatically default
to a null queue. (Note, that in expansion mode a user may want to assign a
null queue in each device). Note, this option requires that the user must select
serial programming and configure the device to be 31 queues, (or less). The
default mode of device programming should not be selected, (default mode
automatically sets up 32 queues, with the memory equally divided between
queues). If Default mode is selected and the user wishes to assign one queue
as the “Null-Q”, extra care must be taken so as not to write data to the “Null-
Q”, this is very important.
previously selected queue. Changing to a null queue will continue to propagate
data in the pipeline to the previous queue’s output. The Null Q can remain
selected until a data becomes available in another queue for reading. The Null-
Q can be utilized in either standard or packet mode.
as and treated as an empty queue, therefore after switching to the null queue
the last word from the previous queue will remain in the output register and the
OV flag will go HIGH, indicating data is not valid.
queue, it is a means to force data through the pipeline to the output. Null Q
selection and operation has no meaning on the write port of the device. Also,
refer to Figure 20, Read Operation and Null Queue Select for diagram.
PAFn FLAG BUS OPERATION
configured for up to 32 queues, each queue having its own almost full status.
An active queue has its flag status output to the discrete flags, FF and PAF, on
the write port. Queues that are not selected for a write operation can have their
PAF status monitored via the PAFn bus. The PAFn flag bus is 8 bits wide, so
that 8 queues at a time can have their status output to the bus. If 9 or more queues
are setup within a device then there are 2 methods by which the device can
share the bus between queues, “Direct” mode and “Polled” mode depending
on the state of the FM (Flag Mode) input during a Master Reset. If 8 or less
queues are setup within a device then each will have its own dedicated output
from the bus. If 8 or less queues are setup in single device mode, it is
recommended to configure the PAFn bus to polled mode as it does not require
using the write address (WRADD).
EXPANDING UP TO 256 QUEUES OR PROVIDING DEEPER QUEUES
mode. In the 32 queue multi-queue device, the WRADD address bus is 8 bits
wide. The 5 Least Significant bits (LSbs) are used to address one of the 32
available queues within a single multi-queue device. The 3 Most Significant bits
IDT72V51546/72V51556 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
Pipelining of data to the output port enables the device to provide 100% bus
Note, that if reads cease at the empty boundary of a queue, then the last word
Null Q operation requires that a user only uses 31 queues in the 32 multi-
A null queue can be selected when no further reads are required from a
Note: If the user switches the read port to the null queue, this queue is seen
The Null queue operation only has significance to the read port of the multi-
The IDT72V51546/72V51556 multi-queue flow-control devices can be
Expansion can take place using either the standard mode or the packet
22
(MSbs) are used when a device is connected in expansion mode with up to
8 devices connected in width expansion, each device having its own 3-bit
address. When logically expanded with multiple parts, each device is statically
setup with a unique chip ID code on the ID pins, ID0, ID1, and ID2. A device
is selected when the 3 Most Significant bits of the WRADD address bus matches
a 3-bit ID code. The maximum logical expansion is 256 queues (32 queues
x 8 devices) or a minimum of 8 queues (1 queue per device x 8 devices), each
of the maximum size of the individual memory device.
flag bus strobe), to address the almost full flag bus during direct mode of
operation.
11, Full Flag Timing Expansion Mode, Figure 13, Output Valid Flag Timing
(In Expansion Mode), and Figure 32, Multi-Queue Expansion Diagram, for
timing diagrams.
BUS MATCHING OPERATION
During a master reset of the multi-queue the state of the three setup pins, BM
(Bus Matching), IW (Input Width) and OW (Output Width) determine the input and
output port bus widths as per the selections shown in Table 3, “Bus Matching
Set-Up”. 9 bit bytes, 18 bit words and 36 bit long words can be written into and
read from the queues provided that at least one of the ports is setup for x36
operation. When writing to or reading from the multi-queue in a bus matching
mode, the device orders data in a “Little Endian” format. See Figure 3, Bus
Matching Byte Arrangement for details.
reads of data widths determined by the write port width. For example, if the input
port is x36 and the output port is x9, then four data reads from a full queue will
be required to cause the full flag to go HIGH (queue not full). Conversely, the
Output Valid flag and Almost Empty flag operations are always based on writes
and reads of data widths determined by the read port. For example, if the input
TABLE 3      BUS-MATCHING SET-UP
port is x18 and the output port is x36, two write operations will be required to
cause the output valid flag of an empty queue to go LOW, output valid (queue
is not empty).
port, therefore the input bus width to all queues is equal (determined by the input
port size) and the output bus width from all queues is equal (determined by the
output port size).
FULL FLAG OPERATION
The FF flag output provides a full status of the queue currently selected on the
write port for write operations. Internally the multi-queue flow-control device
monitors and maintains a status of the full condition of all queues within it, however
Note: The WRADD bus is also used in conjunction with FSTR (almost full
Refer to Table 1, for Write Address bus arrangement. Also, refer to Figure
Bus Matching operation between the input port and output port is available.
The Full flag and Almost Full flag operation is always based on writes and
Note, that the input port serves all queues within a device, as does the output
The multi-queue flow-control device provides a single Full Flag output, FF.
BM
0
1
1
1
1
I W
X
0
0
1
1
x36 DEVICE
OW
COMMERCIAL AND INDUSTRIAL
X
0
1
0
1
TEMPERATURE RANGES
Write Port
x36
x36
x36
x18
x9
Read Port
x36
x18
x36
x36
x9