IDT72V51556L7-5BB8 IDT, Integrated Device Technology Inc, IDT72V51556L7-5BB8 Datasheet - Page 5

• Manufacturer Part Number: IDT72V51556L7-5BB8
• Description: IC FLOW CTRL MULTI QUEUE 256-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72V51556L7-5BB8

• Configuration: Dual
• Density: 2Mb
• Access Time (max): 4ns
• Word Size: 36b
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: BGA
• Clock Freq (max): 133MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.15V
• Operating Supply Voltage (max): 3.6V
• Supply Current: 100mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 256
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V51556L7-5BB8

DETAILED DESCRIPTION
MULTI-QUEUE STRUCTURE
single data output port with up to 32 FIFO queues in parallel buffering between
the two ports. The user can setup between 1 and 32 Queues within the device.
These queues can be configured to utilize the total available memory, providing
the user with full flexibility and ability to configure the queues to be various depths,
independent of one another.
MEMORY ORGANIZATION/ ALLOCATION
256 x36 bits. When the user is configuring the number of queues and individual
queue sizes the user must allocate the memory to respective queues, in units
of blocks, that is, a single queue can be made up from 0 to m blocks, where m
is the total number of blocks available within a device. Also the total size of any
given queue must be in increments of 256 x36. For the IDT72V51546 and
IDT72V51556 the Total Available Memory is 128 and 256 blocks respectively
(a block being 256 x36). Queues can be built from these blocks to make any
size queue desired and any number of queues desired.
BUS WIDTHS
The device provides the user with Bus Matching options such that the input port
and output port can be either x9, x18 or x36 bits wide provided that at least one
of the ports is x36 bits wide, the read and write port widths being set
independently of one another. Because the ports are common to all queues the
width of the queues is not individually set, so that the input width of all queues
are equal and the output width of all queues are equal.
WRITING TO & READING FROM THE MULTI-QUEUE
queue via the write queue select address inputs. Conversely, data being read
from the device read port is read from a queue selected via the read queue select
address inputs. Data can be simultaneously written into and read from the same
queue or different queues. Once a queue is selected for data writes or reads,
the writing and reading operation is performed in the same manner as a
conventional IDT synchronous FIFO, utilizing clocks and enables, there is a
single clock and enable per port. When a specific queue is addressed on the
write port, data placed on the data inputs is written to that queue sequentially
based on the rising edge of a write clock provided setup and hold times are met.
Conversely, data is read on to the output port after an access time from a rising
edge on a read clock.
FIFO operating in standard IDT mode. Write operations can be performed on
the write port provided that the queue currently selected is not full, a full flag output
provides status of the selected queue. The operation of the read port is
comparable to the function of a conventional FIFO operating in FWFT mode.
When a queue is selected on the output port, the next word in that queue will
automatically fall through to the output register. All subsequent words from that
queue require an enabled read cycle. Data cannot be read from a selected
queue if that queue is empty, the read port provides an Output Valid flag indicating
when data read out is valid. If the user switches to a queue that is empty, the
last word from the previous queue will remain on the output register.
queue. Along with the full flag a dedicated almost full flag is provided, this almost
full flag is similar to the almost full flag of a conventional IDT FIFO. The device
provides a user programmable almost full flag for all 32 queues and when a
IDT72V51546/72V51556 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
The IDT multi-queue flow-control device has a single data input port and
The memory is organized into what is known as “blocks”, each block being
The input port is common to all queues within the device, as is the output port.
Data being written into the device via the input port is directed to a discrete
The operation of the write port is comparable to the function of a conventional
As mentioned, the write port has a full flag, providing full status of the selected
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respective queue is selected on the write port, the almost full flag provides status
for that queue. Conversely, the read port has an output valid flag, providing
status of the data being read from the queue selected on the read port. As well
as the output valid flag the device provides a dedicated almost empty flag. This
almost empty flag is similar to the almost empty flag of a conventional IDT FIFO.
The device provides a user programmable almost empty flag for all 32 queues
and when a respective queue is selected on the read port, the almost empty flag
provides status for that queue.
PROGRAMMABLE FLAG BUSSES
valid & almost empty on the read port, there are two flag status busses. An almost
full flag status bus is provided, this bus is 8 bits wide. Also, an almost empty flag
status bus is provided, again this bus is 8 bits wide. The purpose of these flag
busses is to provide the user with a means by which to monitor the data levels
within queues that may not be selected on the write or read port. As mentioned,
the device provides almost full and almost empty registers (programmable by
the user) for each of the 32 queues in the device.
has the option of utilizing anywhere between 1 and 32 queues, therefore the
8 bit flag status busses are multiplexed between the 32 queues, a flag bus can
only provide status for 8 of the 32 queues at any moment, this is referred to as
a “Quadrant”, such that when the bus is providing status of queues 1 through
8, this is quadrant 1, when it is queues 9 through 16, this is quadrant 2 and so
on up to quadrant 4. If less than 32 queues are setup in the device, there are
still 4 quadrants, such that in “Polled” mode of operation the flag bus will still cycle
through 4 quadrants. If for example only 22 queues are setup, quadrants 1 and
2 will reflect status of queues 1 through 8 and 9 through 16 respectively.
Quadrant 3 will reflect the status of queues 17 through 22 on the least significant
6 bits, the most significant 2 bits of the flag bus are don’t care and the 4th quadrant
outputs will be don’t care also.
“Polled” or “Direct”. When operating in polled mode a flag bus provides status
of each quadrant sequentially, that is, on each rising edge of a clock the flag bus
is updated to show the status of each quadrant in order. The rising edge of the
write clock will update the almost full bus and a rising edge on the read clock will
update the almost empty bus. The mode of operation is always the same for both
the almost full and almost empty flag busses. When operating in direct mode, the
quadrant on the flag bus is selected by the user. So the user can actually address
the quadrant to be placed on the flag status busses, these flag busses operate
independently of one another. Addressing of the almost full flag bus is done via
the write port and addressing of the almost empty flag bus is done via the read
port.
PACKET MODE
Packet Mode is user selectable and requires the device to be configured with
both write and read ports as 36 bits wide. In packet mode, users can define
the length of packets or frame by using the two most significant bits of the 36-
bit word. Bit 34 is used to mark the Start of Packet (SOP) and bit 35 is used to
mark the End of Packet (EOP) as shown in Table 5). When writing data into
a given queue, the first word being written is marked, by the user setting bit 34
as the “Start of Packet” (SOP) and the last word written is marked as the “End
of Packet” (EOP) with all words written between the Start of Packet (SOP)
marker (bit 34) and the End of packet (EOP) packet marker (bit 35) constituting
the entire packet. A packet can be any length the user desires, up to the total
available memory in the multi-queue flow-control device. The device monitors
the SOP (bit 34) and looks for the word that contains the EOP (bit 35). The read
In addition to these dedicated flags, full & almost full on the write port and output
In the IDT72V51546/72V51556 multi-queue flow-control devices the user
The flag busses are available in two user selectable modes of operation,
The multi-queue flow-control device also offers a “Packet Mode” operation.
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES