IDT72V51556L7-5BB8 IDT, Integrated Device Technology Inc, IDT72V51556L7-5BB8 Datasheet - Page 2

• Manufacturer Part Number: IDT72V51556L7-5BB8
• Description: IC FLOW CTRL MULTI QUEUE 256-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72V51556L7-5BB8

• Configuration: Dual
• Density: 2Mb
• Access Time (max): 4ns
• Word Size: 36b
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: BGA
• Clock Freq (max): 133MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.15V
• Operating Supply Voltage (max): 3.6V
• Supply Current: 100mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 256
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V51556L7-5BB8

DESCRIPTION:
chip within which anywhere between 1 and 32 discrete FIFO queues can be
setup. All queues within the device have a common data input bus, (write port)
and a common data output bus, (read port). Data written into the write port is
directed to a respective queue via an internal de-multiplex operation, ad-
dressed by the user. Data read from the read port is accessed from a respective
queue via an internal multiplex operation, addressed by the user. Data writes
and reads can be performed at high speeds up to 166MHz, with access times
of 3.7ns. Data write and read operations are totally independent of each other,
a queue maybe selected on the write port and a different queue on the read
port or both ports may select the same queue simultaneously.
selected for write and read operations respectively. Also a Programmable
Almost Full and Programmable Almost Empty flag for each queue is provided.
Two 8 bit programmable flag busses are available, providing status of queues
not selected for write or read operations. When 8 or less queues are configured
in the device these flag busses provide an individual flag per queue, when
more than 8 queues are used, either a Polled or Direct mode of bus operation
provides the flag busses with all queues status.
or 36 bits wide provided that at least one port is 36 bits wide. When Bus Matching
is used the device ensures the logical transfer of data throughput in a Little
Endian manner.
IDT72V51546/72V51556 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
The IDT72V51546/72V51556 multi-queue flow-control devices are single
The device provides Full flag and Output Valid flag status for the queue
Bus Matching is available on this device, either port can be 9 bits, 18 bits
2
for 36 bit input and 36 bit output port sizes. The Packet mode provides the user
with a flag output indicating when at least one (or more) packets of data within a
queue is available for reading. The Packet Ready provides the user with a means
by which to mark the start and end of packets of data being passed through the
queues. The multi-queue device then provides the user with an internally
generated packet ready status per queue.
to program the total number of queues between 1 and 32, the individual queue
depths being independent of each other. The programmable flag positions are
also user programmable. All programming is done via a dedicated serial port.
If the user does not wish to program the multi-queue device, a default option is
available that configures the device in a predetermined manner.
Reset latches in all configuration setup pins and must be performed before
programming of the device can take place. A Partial Reset will reset the read and
write pointers of an individual queue, provided that the queue is selected on both
the write port and read port at the time of partial reset.
fully functional Boundary Scan feature, compliant with IEEE 1149.1 Standard
Test Access Port and Boundary Scan Architecture.
of the functional blocks within the device.
A packet mode of operation is also provided when the device is configured
The user has full flexibility configuring queues within the device, being able
Both Master Reset and Partial Reset pins are provided on this device. A Master
A JTAG test port is provided, here the multi-queue flow-control device has a
See Figure 1, Multi-Queue Flow-Control Device Block Diagram for an outline
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES