IDT72V51556L7-5BB8 IDT, Integrated Device Technology Inc, IDT72V51556L7-5BB8 Datasheet - Page 49

• Manufacturer Part Number: IDT72V51556L7-5BB8
• Description: IC FLOW CTRL MULTI QUEUE 256-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72V51556L7-5BB8

• Configuration: Dual
• Density: 2Mb
• Access Time (max): 4ns
• Word Size: 36b
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: BGA
• Clock Freq (max): 133MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.15V
• Operating Supply Voltage (max): 3.6V
• Supply Current: 100mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 256
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V51556L7-5BB8

Cycle:
*A*
*AA* Quadrant 4 of device 0 is selected for the PAFn bus. The bus is currently providing status of a previously selected quadrant, Quad Y of device X.
*B*
*BB* Queue 31 of device 0 is selected on the write port.
*C*
*CC* PAFn continues to show status of Quad4 D0.
*D*
*DD* PAF[7] goes HIGH to show that D0 Q31 is not almost empty due to the read on cycle *C*.
*E*
*EE* Word, Wy+1 is written into D0 Q31.
*F*
*FF* PAF[7] and the discrete PAF flag go LOW to show the write on cycle *DD* causes Q31 of D0 to again go almost full.
*G*
IDT72V51546/72V51556 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
Device 0
Queue 31 of device 0 is selected for read operations.
The last word in the output register is available on Qout. OE was previously taken LOW so the output bus is in Low-Impedance.
Word, Wx+1 is read out from the previous queue due to the FWFT effect.
The PAFn bus is updated with the quadrant selected on the previous cycle, D0 Quad 4. PAF[7] is LOW showing the status of queue 31.
The PAFn outputs of the device previously selected on the PAFn bus go to High-Impedance.
A new quadrant, Quad 1 of Device 7 is selected for the PAFn bus.
Word, Wd-m+1 is read from Q31 D0 due to the FWFT operation. This read is at the PAFn boundary of queue D0 Q31. This read will cause the PAF[7] output to go from
LOW to HIGH (almost full to not almost full), after a delay t
No read operations occur, REN is HIGH.
The active queue PAF flag of device 0 goes from High-Impedance to Low-Impedance.
Word, Wy is written into D0 Q31.
Queue 2 of Device 6 is selected for write operations.
Word, Wd-m+2 is read out due to FWFT operation.
Word, Wy+2 is written into D0 Q31.
Word, W0 is read from Q0 of D6, selected on cycle *E*, due to FWFT.
Bus
Device 0
WRADD
WADEN
RDADD
RADEN
WCLK
RCLK
ESTR
FSTR
PAFn
PAFn
PAFn
WEN
Prev.
Qout
REN
PAF
Din
OE
t
D
D
QS
t
AS
t
t
X
X
STS
AS
Quad y
Quad y
000 11111
D0Q31
D0 quad4
t
OLZ
*A*
*AA*
000 xxx11
t
Prev. Q
t
t
AH
t
QH
STH
W
AH
X
t
QS
HIGH-Z
t
AS
HIGH - Z
*B*
D0 Q31
Figure 29. PAF n - Direct Mode, Flag Operation
*BB*
t
A
SKEW3
t
t
STS
PAFHZ
t
t
AS
PAFLZ
Prev. Q
t
t
AH
W
QH
111 xxx00
X +1
+ WCLK + tPAF. If t
D7 quad 1
D0Quad4
D0Quad4
*C*
*CC*
t
A
t
1
SKEW3
t
t
AH
STH
49
0xxx xxxx
0xxx xxxx
t
ENS
SKEW3
*D*
t
DS
Word W
D0 Q31
*DD*
is violated add an extra WCLK cycle.
2
t
QS
t
DH
y
D0 Q31
W
t
t
PAF
PAFLZ
D-M+1
110 00010
D6Q2
*E
*
D0Quad4
D0Quad4
t
DS
D0 Q31
*EE*
W
t
y+1
QH
t
HIGH-Z
DH
1xxx xxxx
1xxx xxxx
*F
*
COMMERCIAL AND INDUSTRIAL
t
DS
D0 Q31
t
A
W
*FF*
y+2
W
D0 Q31
t
TEMPERATURE RANGES
DH
D - M + 2
t
ENH
t
t
PAF
D0Quad4
D0Quad40xxx xxxx
*G*
WAF
t
A
0xxx xxxx
D6 Q2
W
5904 drw32
0