IDT72V51556L7-5BB8 IDT, Integrated Device Technology Inc, IDT72V51556L7-5BB8 Datasheet - Page 48

• Manufacturer Part Number: IDT72V51556L7-5BB8
• Description: IC FLOW CTRL MULTI QUEUE 256-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72V51556L7-5BB8

• Configuration: Dual
• Density: 2Mb
• Access Time (max): 4ns
• Word Size: 36b
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: BGA
• Clock Freq (max): 133MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.15V
• Operating Supply Voltage (max): 3.6V
• Supply Current: 100mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 256
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V51556L7-5BB8

Cycle:
*A*
*AA* Queue 24 of Device 5 is selected for read operations.
*B*
*BB* Word, Wa+1 is read from Q17 of D5, due to FWFT operation.
*C*
*CC* Word, Wy from the newly selected queue, Q24 will be read out due to FWFT operation.
*D*
*DD* The PAEn bus changes control to D5, the PAEn outputs of D5 go to Low-Impedance and quadrant 4 is placed onto the outputs. The device of the previously selected
*E*
*EE* Word, Wy+2 is read from Q24 of D5.
*F*
*FF* The PAEn bus updates to show that Q24 of D5 is almost empty based on the reading out of word, Wy+1.
IDT72V51546/72V51556 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
Device 5 PAEn
Queue 24 of Device 5 is selected for write operations.
Word, Wp is written into the previously selected queue.
A quadrant from another device has control of the PAEn bus.
The discrete PAE output of device 5 is currently in High-Impedance and the PAE active flag is controlled by the previously selected device.
Word Wp+1 is written into the previously selected queue.
Word, Wn is written into the newly selected queue, Q24 of D5. This write will cause the PAE flag on the read port to go from LOW to HIGH (not almost empty) after time,
t
Quadrant 4 of Device 5 is selected on the PAEn bus. Q24 of device 5 will therefore have is PAE status output on PAE[0]. There is a single RCLK cycle latency before
the PAEn bus changes to the new selection.
Queue 8 of Device 3 is selected for write operations.
Word Wn+1 is written into Q24 of D5.
quadrant now places its PAEn outputs into High-Impedance to prevent bus contention. Word, Wy+1 is read from Q24 of D5.
The discrete PAE flag will go HIGH to show that Q24 of D5 is not almost empty. Q24 of device 5 will have its PAE status output on PAE[0].
No writes occur.
Quadrant 3 of device 4 is selected on the write port for the PAFn bus.
Word, Wx is written into Q8 of D3.
The discrete PAE flag goes LOW to show that Q24 of D5 is almost empty based on the reading of Wy+1.
SKEW3
Device 5 PAE
Device 5 -Qn
Prev PAEn
Bus PAEn
WADEN
WRADD
RADEN
RDADD
+ RCLK + t
FSTR
WCLK
ESTR
RCLK
REN
WEN
Dn
RAE
D5 Q17
(if t
Wa
t
t
SKEW3
QS
ENS
t
AS
t
QS
100 11000
D5Q24
is violated one extra RCLK cycle will be added.
Previous value loaded on to PAE bus
D5 Q17 Status
Previous value loaded on to PAE bus
t
Wp
AS
*A*
Writes to Previous Q
100
11000
D5Q24
*AA*
t
t
AH
QH
t
AH
t
t
DS
QH
Wp+1
Figure 28. PAE n - Direct Mode, Flag Operation
*B*
1
*BB*
t
DH
t
A
t
t
DS
STS
t
AS
D5 Q24
*C*
2
Wn
101 xxx11
D5 quad 4
Wa+1
D5 Q17
*CC*
t
DH
t
SKEW3
1
t
t
A
48
QS
t
AS
t
t
011 01000
t
AH
RAE
STH
t
ENS
D5 Q24
D3Q8
Wn+1
D5Q24
status
t
PAEZL
*D*
Wy
D5 Q24
*DD*
t
t
AH
t
2
QH
t
ENH
A
t
t
RAE
PAEHZ
*E*
Wy+1
D5 Q24
*EE*
t
STS
D5Quad 4
t
xxxx xxx1
t
ENS
D5Quad 4
A
xxxx xxx1
t
AS
100 xxx10
D4 quad 3
Wx
D3 Q8
*F*
COMMERCIAL AND INDUSTRIAL
Wy+2
D5 Q24
*FF*
t
AH
t
t
STH
ENH
t
A
TEMPERATURE RANGES
t
t
PAE
ENH
t
RAE
xxxx xxx0
D5Quad4
xxxx xxx0
D5Quad4
Wy+3
D5 Q24
5904 drw31