EVB9221-MINI SMSC, EVB9221-MINI Datasheet - Page 130

• Manufacturer Part Number: EVB9221-MINI
• Description: EVALUATION BOARD LAN9221-ABZJ
• Manufacturer: SMSC

Specifications of EVB9221-MINI

• Main Purpose: Interface, Ethernet Controller (PHY and MAC)
• Embedded: No
• Utilized Ic / Part: LAN9221
• Primary Attributes: 1 Port, 100BASE-TX/10BASE-T
• Secondary Attributes: 16-Bit, HP Auto-MDIX, Full and Half Duplex Support, 32-Bit CRC
• Processor To Be Evaluated: LAN9221
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1074

Revision 2.7 (03-15-10)
6.2.2
RX Status FIFO
TX Status FIFO
RX Data FIFO
READING...
RX_DROP
REGISTER NAME
AFTER
MAC_CSR_DATA
MAC_CSR_CMD
E2P_DATA
RX_DROP
AFC_CFG
E2P_CMD
Special Restrictions on Back-to-Back Read Cycles
There are also restrictions on specific back-to-back read operations. These restrictions concern
reading specific registers after reading resources that have side effects. In many cases there is a delay
between reading the LAN9221/LAN9221i, and the subsequent indication of the expected change in the
control register values.
In order to prevent the host from reading stale data on back-to-back reads, minimum wait periods have
been established. These periods are specified in
processor is required to wait the specified period of time between read operations of specific
combinations of resources. The wait period is dependant upon the combination of registers being read.
Performing "dummy" reads of the BYTE_TEST register is a convenient way to guarantee that the
minimum wait time restriction is met.
required for back-to-back read operations. The number of BYTE_TEST reads in this table is based on
the minimum timing for Tcycle (45ns). For microprocessors with slower busses the number of reads
may be reduced as long as the total time is equal to, or greater than the time specified in the table.
Dummy reads of the BYTE_TEST register are not required as long as the minimum time period is met.
WAIT FOR THIS MANY
Table 6.1 Read After Write Timing Rules (continued)
NS…
135
135
135
180
Table 6.2 Read After Read Timing Rules
FOLLOWING ANY WRITE CYCLE
MINIMUM WAIT TIME FOR READ
DATASHEET
(IN NS)
Table 6.2
45
45
45
45
45
0
(ASSUMING Tcycle OF 45NS)
130
OR PERFORM THIS MANY
READS OF BYTE_TEST…
High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O
Table 6.2, "Read After Read Timing
also shows the number of dummy reads that are
3
3
3
4
(ASSUMING T
NUMBER OF BYTE_TEST
BEFORE READING...
READS
RX_FIFO_INF
RX_FIFO_INF
TX_FIFO_INF
SMSC LAN9221/LAN9221i
CYCLE
0
1
1
1
1
1
RX_DROP
Rules". The host
OF 45NS)
Datasheet