EVB9221-MINI SMSC, EVB9221-MINI Datasheet - Page 38

• Manufacturer Part Number: EVB9221-MINI
• Description: EVALUATION BOARD LAN9221-ABZJ
• Manufacturer: SMSC

Specifications of EVB9221-MINI

• Main Purpose: Interface, Ethernet Controller (PHY and MAC)
• Embedded: No
• Utilized Ic / Part: LAN9221
• Primary Attributes: 1 Port, 100BASE-TX/10BASE-T
• Secondary Attributes: 16-Bit, HP Auto-MDIX, Full and Half Duplex Support, 32-Bit CRC
• Processor To Be Evaluated: LAN9221
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1074

Revision 2.7 (03-15-10)
3.8
FPORTEND=0
FPORTEND=1
FPORTEND=0
FPORTEND=1
FPORTEND=0
FPORTEND=1
PORTEND=0
PORTEND=1
FSELEND=0
FSELEND=0
FSELEND=1
FSELEND=1
FSELEND=0
FSELEND=0
FSELEND=1
FSELEND=1
The General Purpose Timer is a programmable block that can be used to generate periodic host
interrupts. The resolution of this timer is 100uS.
The GP Timer loads the GPT_CNT Register with the value in the GPT_LOAD field and begins counting
down when the TIMER_EN bit is set to a ‘1.’ On a reset, or when the TIMER_EN bit changes from
set ‘1’ to cleared ‘0,’ the GPT_LOAD field is initialized to FFFFh. The GPT_CNT register is also
initialized to FFFFh on a reset. Software can write the pre-load value into the GPT_LOAD field at any
time; e.g., before or after the TIMER_EN bit is asserted. The GPT Enable bit TIMER_EN is located in
the GPT_CFG register.
Once enabled, the GPT counts down either until it reaches 0000h or until a new pre-load value is
written to the GPT_LOAD field. At 0000h, the counter wraps around to FFFFh, asserts the GPT
interrupt status bit and the IRQ signal if the GPT_INT_EN bit is set, and continues counting. The GPT
interrupt status bit is in the INT_STS Register. The GPT_INT hardware interrupt can only be set if the
GPT_INT_EN bit is set. GPT_INT is a sticky bit (R/WC); i.e., once the GPT_INT bit is set, it can only
be cleared by writing a ‘1’ to the bit.
General Purpose Timer (GP Timer)
A1=1
A1=0
A1=1
A1=0
A1=1
A1=0
A1=1
A1=0
A1=1
A1=0
A1=1
A1=0
A1=1
A1=0
A1=1
A1=0
Table 3.8 Endian Ordering Logic Operation
FIFO Access via Data
FIFO Port (00h-3Ch)
D[15:8]
Host Data Bus
3
1
0
2
3
1
0
2
1
3
2
0
1
3
2
0
DATASHEET
D[7:0]
2
0
1
3
2
0
1
3
0
2
3
1
0
2
3
1
38
High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O
Direct FIFO Access via
D[15:8]
3
1
3
1
0
2
0
2
1
3
1
3
2
0
2
0
Host Data Bus
FIFO_SEL
D[7:0]
2
0
2
0
1
3
1
3
0
2
0
2
3
1
3
1
D[15:8]
SMSC LAN9221/LAN9221i
Host Data Bus
3
1
3
1
3
1
3
1
1
3
1
3
1
3
1
3
CSR Access
D[7:0]
Datasheet
2
0
2
0
2
0
2
0
0
2
0
2
0
2
0
2