EVB9221-MINI SMSC, EVB9221-MINI Datasheet - Page 131

• Manufacturer Part Number: EVB9221-MINI
• Description: EVALUATION BOARD LAN9221-ABZJ
• Manufacturer: SMSC

Specifications of EVB9221-MINI

• Main Purpose: Interface, Ethernet Controller (PHY and MAC)
• Embedded: No
• Utilized Ic / Part: LAN9221
• Primary Attributes: 1 Port, 100BASE-TX/10BASE-T
• Secondary Attributes: 16-Bit, HP Auto-MDIX, Full and Half Duplex Support, 32-Bit CRC
• Processor To Be Evaluated: LAN9221
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1074

High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O
Datasheet
SMSC LAN9221/LAN9221i
6.3
SYMBOL
t
t
t
t
cycle
t
t
t
csdv
t
t
csh
asu
don
doff
doh
csl
nCS, nRD
ah
A[7:1]
Data Bus
PIO reads can be used to access CSRs or RX Data and RX/TX status FIFOs. In this mode, counters
in the CSRs are latched at the beginning of the read cycle. Read data is valid as indicated in the timing
diagram. PIO reads can be performed using Chip Select (nCS) or Read Enable (nRD). Either or both
of these control signals must go high between cycles for the period specified.
Note: Some registers have restrictions on the timing of back-to-back, write-read and read-read
Note: The “Data Bus” width is 16 bits
Note 6.2
Note: A PIO Read cycle begins when both nCS and nRD are asserted. The cycle ends when either
PIO Reads
DESCRIPTION
Read Cycle Time
nCS, nRD Assertion Time
nCS, nRD Deassertion Time
nCS, nRD Valid to Data Valid
Address Setup to nCS, nRD Valid
Address Hold Time
Data Buffer Turn On Time
Data Buffer Turn Off Time
Data Output Hold Time
cycles.
or both nCS and nRD are deasserted. They may be asserted and deasserted in any order.
When VDDVARIO is 3.3V or 2.5V, the maximum T
1.8V, the maximum T
Figure 6.2 PIO Read Cycle Timing
Table 6.3 PIO Read Timing
doff
DATASHEET
time is 9ns.
131
MIN
45
32
13
0
0
0
0
doff
time is 7ns. When VDDVARIO is
TYP
Note 6.2
MAX
Revision 2.7 (03-15-10)
30
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns