EVB9221-MINI SMSC, EVB9221-MINI Datasheet - Page 89
EVB9221-MINI
Manufacturer Part Number
EVB9221-MINI
Description
EVALUATION BOARD LAN9221-ABZJ
Manufacturer
SMSC
Datasheet
1.LAN9221-ABZJ.pdf
(152 pages)
Specifications of EVB9221-MINI
Main Purpose
Interface, Ethernet Controller (PHY and MAC)
Embedded
No
Utilized Ic / Part
LAN9221
Primary Attributes
1 Port, 100BASE-TX/10BASE-T
Secondary Attributes
16-Bit, HP Auto-MDIX, Full and Half Duplex Support, 32-Bit CRC
Processor To Be Evaluated
LAN9221
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
638-1074
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High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O
Datasheet
SMSC LAN9221/LAN9221i
5.3.9
27-25
23-21
16-19
BITS
15-2
31
30
29
28
24
20
1
Reserved
Reserved
FIFO Port Endian Ordering (FPORTEND). This control bit determines the
endianess of RX and TX data FIFO host accesses when accessed through
the RX/TX Data FIFO ports, including the alias addresses (any access from
00h to 3Ch). When this bit is cleared, data FIFO port accesses utilize little
endian byte ordering. When this bit is set, data FIFO port accesses utilize
big endian byte ordering. Please refer to section
Endian Support," on page 35
Direct FIFO Access Endian Ordering (FSELEND). This control bit
determines the endianess of RX and TX data FIFO host accesses when
accessed using the FIFO_SEL signal. When this bit is cleared, FIFO_SEL
accesses utilize little endian byte ordering. When this bit is set, FIFO_SEL
accesses utilize big endian byte ordering. Please refer to section
3.7.3, "Mixed Endian Support," on page 35
feature.
Reserved
AMDIX_EN Strap State. This read-only bit reflects the state of the
AMDIX_EN strap pin (pin 73). This pin can be overridden by PHY Registers
27.15 and 27.13
Reserved
Must Be One (MBO). This bit must be set to “1” for normal device
operation.
TX FIFO Size (TX_FIF_SZ). Sets the size of the TX FIFOs in 1KB values
to a maximum of 14KB. The TX Status FIFO consumes 512 bytes of the
space allocated by TX_FIF_SIZ, and the TX data FIFO consumes the
remaining space specified by TX_FIF_SZ. The minimum size of the TX
FIFOs is 2KB (TX data and status combined). The TX data FIFO is used for
both TX data and TX commands.
The RX Status and data FIFOs consume the remaining space, which is
equal to 16KB – TX_FIF_SIZ. See
Configurable FIFO Memory Allocation," on page 91
Reserved
Soft Reset Timeout (SRST_TO).
is not in the operational state (RX_CLK and TX_CLK running), the reset will not
complete and the soft reset operation will timeout and this bit will be set to a ‘1’. The
host processor must correct the problem and issue another soft reset.
HW_CFG—Hardware Configuration Register
Note: The transmitter and receiver must be stopped before writing to this register. Refer to
Offset:
3.12.8, "Stopping and Starting the Transmitter," on page 62
Starting the Receiver," on page 67
for more information on this feature.
DESCRIPTION
74h
If a software reset is attempted when the PHY
Section 5.3.9.1, "Allowable settings for
DATASHEET
for more information on this
89
for details on stopping the transmitter and receiver.
Section 3.7.3, "Mixed
for more information.
Size:
Section
and
32 bits
Section 3.13.4, "Stopping and
NASR
NASR
TYPE
R/W
R/W
R/W
R/W
RO
RO
RO
RO
RO
RO
RO
Revision 2.7 (03-15-10)
DEFAULT
AMDIX
Strap
Pin
5h
0
0
0
0
-
-
-
-
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