KDC5612EVAL Intersil, KDC5612EVAL Datasheet - Page 16

• Manufacturer Part Number: KDC5612EVAL
• Description: DAUGHTER CARD FOR KAD5612
• Manufacturer: Intersil
• Series: FemtoCharge™r

Specifications of KDC5612EVAL

• Number Of Adc's: 2
• Number Of Bits: 12
• Sampling Rate (per Second): 250M
• Data Interface: Parallel
• Inputs Per Adc: 1 Differential
• Input Range: 1.47 Vpp
• Power (typ) @ Conditions: 429mW @ 250MSPS
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: KAD5612P-25, KMB001 Motherboard
• For Use With: KMB001LEVAL - MOTHERBOARD FOR LVDS ADC CARD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

An RF transformer will give the best noise and distortion
performance for wideband and/or high intermediate
frequency (IF) inputs. Two different transformer input
schemes are shown in Figures 27 and 28.
This dual transformer scheme is used to improve
common-mode rejection, which keeps the common-mode
level of the input matched to VCM. The value of the shunt
resistor should be determined based on the desired load
impedance. The differential input resistance of the
KAD5612P is 1000Ω.
The SHA design uses a switched capacitor input stage (see
Figure 42), which creates current spikes when the sampling
capacitance is reconnected to the input voltage. This causes
a disturbance at the input which must settle before the next
sampling point. Lower source impedance will result in faster
settling and improved performance. Therefore a 1:1
transformer and low shunt resistance are recommended for
optimal performance.
FIGURE 28. TRANSMISSION-LINE TRANSFORMER INPUT
FIGURE 27. TRANSFORMER INPUT FOR GENERAL
1000pF
1000pF
1000pF
1.8
1.4
1.0
0.6
0.2
ADT1-1WT
FIGURE 26. ANALOG INPUT RANGE
ADTL1-12
PURPOSE APPLICATIONS
0.725V
ADTL1-12
ADT1-1WT
16
INP
0.1µF
0.1µF
INN
VCM
0.535V
VCM
KAD5612P
KAD5612P
VCM
KAD5612P
A differential amplifier, as shown in Figure 29, can be used in
applications that require dc-coupling. In this configuration
the amplifier will typically dominate the achievable SNR and
distortion performance.
Clock Input
The clock input circuit is a differential pair (see Figure 43).
Driving these inputs with a high level (up to 1.8V
input) sine or square wave will provide the lowest jitter
performance. A transformer with 4:1 impedance ratio will
provide increased drive levels.
The recommended drive circuit is shown in Figure 30. A duty
range of 40% to 60% is acceptable. The clock can be driven
single-ended, but this will reduce the edge rate and may
impact SNR performance. The clock inputs are internally
self-biased to AVDD/2 to facilitate AC coupling.
A selectable 2x frequency divider is provided in series with
the clock input. The divider can be used in the 2x mode with
a sample clock equal to twice the desired sample rate. This
allows the use of the Phase Slip feature, which enables
synchronization of multiple ADCs.
The clock divider can also be controlled through the SPI
port, which overrides the CLKDIV pin setting. Details on this
are contained in “Serial Peripheral Interface” on page 19.
49.9O
0.22µF
200pF
Ω
FIGURE 29. DIFFERENTIAL AMPLIFIER INPUT
FIGURE 30. RECOMMENDED CLOCK DRIVE
CLKDIV PIN
69.8O
69.8O
AVDD
AVSS
Float
TC4-1W
TABLE 1. CLKDIV PIN SETTINGS
Ω
100O
100O
Ω
Ω
Ω
348O
348O
1000pF
CM
Ω
Ω
0.1µF
DIVIDE RATIO
25O
25O
Ω
Ω
217O
200pF
200pF
200O
2
1
4
Ω
Ω
September 9, 2009
P-P
KAD5612P
on each
FN6803.2
CLKP
CLKN
VCM