KDC5612EVAL Intersil, KDC5612EVAL Datasheet - Page 7

• Manufacturer Part Number: KDC5612EVAL
• Description: DAUGHTER CARD FOR KAD5612
• Manufacturer: Intersil
• Series: FemtoCharge™r

Specifications of KDC5612EVAL

• Number Of Adc's: 2
• Number Of Bits: 12
• Sampling Rate (per Second): 250M
• Data Interface: Parallel
• Inputs Per Adc: 1 Differential
• Input Range: 1.47 Vpp
• Power (typ) @ Conditions: 429mW @ 250MSPS
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: KAD5612P-25, KMB001 Motherboard
• For Use With: KMB001LEVAL - MOTHERBOARD FOR LVDS ADC CARD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

CLKOUTN
CLKOUTP
D[11:0]P
D[11:0]N
Timing Diagrams
Switching Specifications
NOTES:
10. The SPI may operate asynchronously with respect to the ADC sample clock.
11. The CSB setup time increases in sleep mode due to the reduced power state, CSB setup time in Nap mode is equal to normal mode CSB setup
ADC
Aperture Delay
RMS Aperture Jitter
Output Clock to Data Propagation Delay,
LVDS Mode (Note 8)
Output Clock to Data Propagation Delay,
CMOS Mode (Note 8)
Latency (Pipeline Delay)
Overvoltage Recovery
SPI INTERFACE (Notes 9, 10)
SCLK Period
SCLK Duty Cycle (t
CSB↓ to SCLK↑ Setup Time
CSB↑ after SCLK↑ Hold Time
Data Valid to SCLK↑ Setup Time
Data Valid after SCLK↑ Hold Time
Data Valid after SCLK↓ Time
Data Invalid after SCLK↑ Time
Sleep Mode CSB↓ to SCLK↑ Setup Time
(Note 11)
CLKN
CLKP
7. The Tri-Level Inputs internal switching thresholds are approximately 0.43V and 1.34V. It is advised to float the inputs, tie to ground or AVDD
8. The input clock to output clock delay is a function of sample rate, using the output clock to latch the data simplifies data capture for most
9. SPI Interface timing is directly proportional to t
FIGURE 1. LVDS TIMING DIAGRAM—DDR (see “Digital
INN
INP
depending on desired function.
applications. Contact factory for more info if needed.
time (4ns min at 250Msps).
t
CPD
t
A
SAMPLE N
A DATA
N-L
PARAMETER
Outputs” on page 17)
t
PD
B DATA
N-L
t
DC
HI
/t
CLK
LATENCY = L CYCLES
A DATA
N-L + 1
or t
LO
B DATA
N-L + 1
7
/t
CLK
A DATA
N-L + 2
)
Rising Edge
Falling Edge
Rising Edge
Falling Edge
Write Operation
Read Operation
Read or Write
Read or Write
Read or Write
Write
Write
Read
Read
Read or Write in Sleep Mode
B DATA
N-L + 2
S,
the ADC sample period (4ns at 250Msps)
CONDITION
A DATA
N
KAD5612P
CLKOUT
D[11:0]
SYMBOL
CLKP
CLKN
FIGURE 2. CMOS TIMING DIAGRAM—DDR (“Digital
t
t
t
t
t
t
t
DHW
DSW
t
t
t
t
OVR
DVR
DHR
CLK
CLK
INN
DC
DC
DC
DC
INP
t
t
t
t
j
L
A
A
S
H
S
t
CPD
t
A
SAMPLE N
A DATA
N-L
Outputs” on page 17)
-260
-160
-220
-310
MIN
150
16
66
25
t
1
3
1
3
3
PD
B DATA
N-L
t
DC
LATENCY = L CYCLES
A DATA
N-L + 1
TYP
375
-50
-10
-90
7.5
60
10
50
1
B DATA
N-L + 1
A DATA
N-L + 2
MAX
16.5
120
230
200
110
75
B DATA
N-L + 2
September 9, 2009
(Note 9)
UNITS
cycles
cycles
cycles
cycles
cycles
cycles
cycles
cycles
cycles
cycles
ps
ps
ps
ps
ps
µs
%
fs
FN6803.2
A DATA
N