KDC5612EVAL Intersil, KDC5612EVAL Datasheet - Page 25

DAUGHTER CARD FOR KAD5612

KDC5612EVAL

Manufacturer Part Number
KDC5612EVAL
Description
DAUGHTER CARD FOR KAD5612
Manufacturer
Intersil
Series
FemtoCharge™r

Specifications of KDC5612EVAL

Number Of Adc's
2
Number Of Bits
12
Sampling Rate (per Second)
250M
Data Interface
Parallel
Inputs Per Adc
1 Differential
Input Range
1.47 Vpp
Power (typ) @ Conditions
429mW @ 250MSPS
Voltage Supply Source
Single Supply
Operating Temperature
-40°C ~ 85°C
Utilized Ic / Part
KAD5612P-25, KMB001 Motherboard
For Use With
KMB001LEVAL - MOTHERBOARD FOR LVDS ADC CARD
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
INPUT
Equivalent Circuits
INP
INN
ADDR
C6-FF
(Hex)
C0
C1
C2
C3
C4
C5
AVDD
FIGURE 44. TRI-LEVEL DIGITAL INPUTS
AVDD
AVDD
user_patt1_msb
user_patt2_msb
user_patt1_lsb
user_patt2_lsb
PARAMETER
Reserved
1000O Ω
reserved
NAME
test_io
FIGURE 42. ANALOG INPUTS
280O Ω
75kO
75kO
AVDD
Ω
Ω
Φ
F 1
Φ
F 1
User Test Mode [1:0]
(MSB)
BIT 7
B15
B15
25
B7
B7
10 = Reserved
11 = Reserved
01 = Alternate
75kO
00 = Single
AVDD
Ω
CSAMP
CSAMP
1.6pF
1.6pF
Φ
F 2
Φ
F 2
BIT 6
B14
B14
B6
B6
75kO
TABLE 17. SPI MEMORY MAP (Continued)
AVDD
Ω
BIT 5
Φ
F 3
Φ
F 3
B13
B13
B5
B5
PIPELINE
PIPELINE
CHARGE
CHARGE
TO
TO
SENSE
LOGIC
TO
KAD5612P
BIT 4
B12
B12
B4
B4
Reserved
Reserved
4 = Checker Board
1 = Midscale Short
CLKP
CLKN
BIT 3
2 = +FS Short
3 = -FS Short
5 = reserved
6 = reserved
B11
B11
B3
B3
0 = Off
(20k PULL-UP
INPUT
ON RESETN
Output Test Mode [3:0]
ONLY)
AVDD
AVDD
OVDD
BIT 2
B10
B10
B2
B2
FIGURE 45. DIGITAL INPUTS
11kO
11kO
FIGURE 43. CLOCK INPUTS
Ω
Ω
7 = One/Zero Word
BIT 1
280Ω
9-15 = reserved
B1
B9
B1
B9
20kΩ
8 = User Input
AVDD
Toggle
Ω
OVDD
18kO
18kO
(LSB)
BIT 0
Ω
Ω
B0
B8
B0
B8
OVDD
AVDD
VALUE
(Hex)
DEF.
00h
00h
00h
00h
00h
00h
LOGIC
September 9, 2009
GENERATION
TO
CLOCK-
PHASE
INDEXED/
GLOBAL
TO
FN6803.2
G
G
G
G
G
G

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