PIC18LF25J11-I/SO Microchip Technology, PIC18LF25J11-I/SO Datasheet - Page 128
PIC18LF25J11-I/SO
Manufacturer Part Number
PIC18LF25J11-I/SO
Description
IC PIC MCU FLASH 32K 2V 28-SOIC
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.MA180023.pdf
(528 pages)
2.PIC18LF24J10-ISS.pdf
(32 pages)
3.PIC18F24J11-ISS.pdf
(14 pages)
Specifications of PIC18LF25J11-I/SO
Core Size
8-Bit
Program Memory Size
32KB (16K x 16)
Oscillator Type
Internal
Core Processor
PIC
Speed
48MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
FLASH
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 10x10b
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Controller Family/series
PIC18
No. Of I/o's
16
Ram Memory Size
3776Byte
Cpu Speed
48MHz
No. Of Timers
5
No. Of Pwm
RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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PIC18F46J11 FAMILY
REGISTER 9-3:
REGISTER 9-4:
DS39932C-page 128
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-2
bit 1
bit 0
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-3
bit 2-1
bit 0
Note 1:
U-0
U-0
—
—
To enable the actual RTCC output, the RTCOE (RTCCFG<2>) bit needs to be set.
Unimplemented: Read as ‘0’
RTSECSEL<1:0>: RTCC Seconds Clock Output Select bits
11 = Reserved; do not use
10 = RTCC source clock is selected for the RTCC pin (can be INTRC or T1OSC, depending on the
01 = RTCC seconds clock is selected for the RTCC pin
00 = RTCC alarm pulse is selected for the RTCC pin
PMPTTL: PMP Module TTL Input Buffer Select bit
1 = PMP module uses TTL input buffers
0 = PMP module uses Schmitt Trigger input buffers
Unimplemented: Read as ‘0’
SPI2OD: SPI2 Open-Drain Output Enable bit
1 = Open-drain capability enabled
0 = Open-drain capability disabled
SPI1OD: SPI1 Open-Drain Output Enable bit
1 = Open-drain capability enabled
0 = Open-drain capability disabled
U-0
—
U-0
—
RTCOSC (CONFIG3L<1>) setting)
ODCON3: PERIPHERAL OPEN-DRAIN CONTROL REGISTER 3 (BANKED F40h)
PADCFG1: PAD CONFIGURATION CONTROL REGISTER 1 (BANKED F3Ch)
W = Writable bit
‘1’ = Bit is set
W = Writable bit
‘1’ = Bit is set
U-0
—
U-0
—
U-0
—
U-0
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U-0
—
U-0
—
RTSECSEL1
(1)
R/W-0
U-0
—
(1)
RTSECSEL0
x = Bit is unknown
© 2009 Microchip Technology Inc.
x = Bit is unknown
SPI2OD
R/W-0
R/W-0
(1)
PMPTTL
SPI1OD
R/W-0
R/W-0
bit 0
bit 0
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