PIC18LF25J11-I/SO Microchip Technology, PIC18LF25J11-I/SO Datasheet - Page 417

• Manufacturer Part Number: PIC18LF25J11-I/SO
• Description: IC PIC MCU FLASH 32K 2V 28-SOIC
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18LF25J11-I/SO

• Core Size: 8-Bit
• Program Memory Size: 32KB (16K x 16)
• Oscillator Type: Internal
• Core Processor: PIC
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 10x10b
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Controller Family/series: PIC18
• No. Of I/o's: 16
• Ram Memory Size: 3776Byte
• Cpu Speed: 48MHz
• No. Of Timers: 5
• No. Of Pwm: RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

BNC
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
© 2009 Microchip Technology Inc.
Q Cycle Activity:
If Jump:
If No Jump:
Before Instruction
After Instruction
operation
Decode
Decode
No
PC
If Carry
If Carry
Q1
Q1
PC
PC
Read literal
Read literal
operation
Branch if Not Carry
BNC
-128 ≤ n ≤ 127
if Carry bit is ‘0’,
(PC) + 2 + 2n → PC
None
If the Carry bit is ‘0’, then the program
will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
1
1(2)
HERE
1110
No
Q2
‘n’
Q2
‘n’
=
=
=
=
=
n
address (HERE)
0;
address (Jump)
1;
address (HERE + 2)
0011
BNC
operation
Process
Process
Data
Data
No
Q3
Q3
Jump
nnnn
operation
operation
Write to
PC
No
No
Q4
Q4
nnnn
PIC18F46J11 FAMILY
BNN
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
If Jump:
If No Jump:
Before Instruction
After Instruction
operation
Decode
Decode
No
PC
If Negative
If Negative
Q1
Q1
PC
PC
Read literal
Read literal
operation
Branch if Not Negative
BNN
-128 ≤ n ≤ 127
if Negative bit is ‘0’,
(PC) + 2 + 2n → PC
None
If the Negative bit is ‘0’, then the
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
1
1(2)
HERE
1110
No
Q2
‘n’
Q2
‘n’
=
=
=
=
=
n
address (HERE)
0;
address (Jump)
1;
address (HERE + 2)
0111
BNN
operation
Process
Process
Data
Data
No
Q3
Q3
DS39932C-page 417
Jump
nnnn
operation
operation
Write to
PC
No
No
Q4
Q4
nnnn