PIC18F25J11-I/ML Microchip Technology, PIC18F25J11-I/ML Datasheet - Page 216

• Manufacturer Part Number: PIC18F25J11-I/ML
• Description: IC PIC MCU FLASH 32K 2V 28-QFN
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F25J11-I/ML

• Core Size: 8-Bit
• Program Memory Size: 32KB (16K x 16)
• Core Processor: PIC
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Controller Family/series: PIC18
• No. Of I/o's: 16
• Ram Memory Size: 3.6875KB
• Cpu Speed: 48MHz
• No. Of Timers: 5
• Interface: EUSART, I2C, SPI
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3776 B
• Interface Type: EUSART, I2C, SPI
• Maximum Clock Frequency: 48 MHz
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM183022, DM183032, DV164136, MA180023
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 10 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC18F46J11 FAMILY
FIGURE 14-5:
14.5.5
When Timer3 gate value status is utilized, it is possible
to read the most current level of the gate control value.
The value is stored in the T3GVAL bit in the T3GCON
register. The T3GVAL bit is valid even when the Timer3
gate is not enabled (TMR3GE bit is cleared).
DS39932C-page 216
TMR3GIF
TMR3GE
T3GSPM
T3DONE
T3GPOL
T3GVAL
T3GGO/
T3G_IN
T3GTM
Timer3
T1CKI
TIMER3 GATE VALUE STATUS
TIMER3 GATE SINGLE PULSE AND TOGGLE COMBINED MODE
N
Cleared by Software
Counting Enabled on
Rising Edge of T3G
Set by Software
N + 1
Falling Edge of T3GVAL
N + 2
14.5.6
When the Timer3 gate event interrupt is enabled, it is
possible to generate an interrupt upon the completion
of a gate event. When the falling edge of T3GVAL
occurs, the TMR3GIF flag bit in the PIR3 register will be
set. If the TMR3GIE bit in the PIE3 register is set, then
an interrupt will be recognized.
The TMR3GIF flag bit operates even when the Timer3
gate is not enabled (TMR3GE bit is cleared).
Set by Hardware on
N + 3
TIMER3 GATE EVENT INTERRUPT
© 2009 Microchip Technology Inc.
N + 4
Cleared by Hardware on
Falling Edge of T3GVAL
Cleared by
Software