PIC18F25J11-I/ML Microchip Technology, PIC18F25J11-I/ML Datasheet - Page 51
![IC PIC MCU FLASH 32K 2V 28-QFN](/photos/6/81/68120/150-28-qfn_sml.jpg)
PIC18F25J11-I/ML
Manufacturer Part Number
PIC18F25J11-I/ML
Description
IC PIC MCU FLASH 32K 2V 28-QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.MA180023.pdf
(528 pages)
2.PIC18LF24J10-ISS.pdf
(32 pages)
3.PIC18F24J11-ISS.pdf
(14 pages)
Specifications of PIC18F25J11-I/ML
Core Size
8-Bit
Program Memory Size
32KB (16K x 16)
Core Processor
PIC
Speed
48MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
FLASH
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2.15 V ~ 3.6 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Controller Family/series
PIC18
No. Of I/o's
16
Ram Memory Size
3.6875KB
Cpu Speed
48MHz
No. Of Timers
5
Interface
EUSART, I2C, SPI
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3776 B
Interface Type
EUSART, I2C, SPI
Maximum Clock Frequency
48 MHz
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM183022, DM183032, DV164136, MA180023
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 10 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F25J11-I/ML
Manufacturer:
MICROCHIP
Quantity:
4 000
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3.6.7
This section gives the typical sequence for using the
Deep Sleep mode. Optional steps are indicated, and
additional information is given in notes at the end of the
procedure.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. If using an RTCC alarm for wake-up, wait until
11. Enter Deep Sleep mode by setting the DSEN bit
12. Once a wake-up event occurs, the device will
13. Determine if the device exited Deep Sleep by
14. Clear the Deep Sleep bit, DS (WDTCON<3>).
15. Determine the wake-up source by reading the
16. Determine if a DSBOR event occurred during
17. Read the DSGPR0 and DSGPR1 context save
18. Clear the RELEASE bit (DSCONL<0>).
© 2009 Microchip Technology Inc.
Note 1: DSWDT
Enable DSWDT (optional).
Configure DSWDT clock source (optional).
Enable DSBOR (optional).
Enable RTCC (optional).
Configure the RTCC peripheral (optional).
Configure the ULPWU peripheral (optional).
Enable the INT0 Interrupt (optional).
Context save SRAM data by writing to the
DSGPR0 and DSGPR1 registers (optional).
Set the REGSLP bit (WDTCON<7>) and clear
the IDLEN bit (OSCCON<7>).
the RTCSYNC (RTCCFG<4>) bit is clear.
(DSCONH<7>) and issuing a SLEEP instruction.
These two instructions must be executed back
to back.
perform a POR reset sequence. Code execution
resumes at the device’s Reset vector.
reading the Deep Sleep bit, DS (WDTCON<3>).
This bit will be set if there was an exit from Deep
Sleep mode.
DSWAKEH and DSWAKEL registers.
Deep Sleep mode by reading the DSBOR bit
(DSCONL<1>).
registers (optional).
2: The DSWDT and RTCC clock sources
3: For more information, see Section 16.0
4: For more information on configuring this
TYPICAL DEEP SLEEP SEQUENCE
through the devices’ Configuration bits.
For more information, see Section 25.1
“Configuration Bits”.
are selected through the devices’ Con-
figuration bits. For more information, see
Section 25.1 “Configuration Bits”.
“Real-Time
(RTCC)”.
peripheral,
Low-Power Wake-up”.
and
see
Clock
(3)
DSBOR
(1)
(1)
Section 3.7
and
are
(4)
Calendar
enabled
(3)
(2)
“Ultra
(4)
PIC18F46J11 FAMILY
3.6.8
If during Deep Sleep the device is subjected to unusual
operating conditions, such as an Electrostatic Dis-
charge (ESD) event, it is possible that the internal
circuit states used by the Deep Sleep module could
become corrupted. If this were to happen, the device
may exhibit unexpected behavior, such as a failure to
wake back up.
In order to prevent this type of scenario from occurring,
the
self-monitoring capability. During Deep Sleep, critical
internal nodes are continuously monitored in order to
detect possible Fault conditions (which would not
ordinarily occur). If a Fault condition is detected, the
circuitry will set the DSFLT status bit (DSWAKEL<7>)
and automatically wake the microcontroller from Deep
Sleep, causing a POR Reset.
During Deep Sleep, the Fault detection circuitry is
always enabled and does not require any specific
configuration prior to entering Deep Sleep.
Deep
DEEP SLEEP FAULT DETECTION
Sleep
module
includes
DS39932C-page 51
automatic
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