PIC18F25J11-I/ML Microchip Technology, PIC18F25J11-I/ML Datasheet - Page 304
![IC PIC MCU FLASH 32K 2V 28-QFN](/photos/6/81/68120/150-28-qfn_sml.jpg)
PIC18F25J11-I/ML
Manufacturer Part Number
PIC18F25J11-I/ML
Description
IC PIC MCU FLASH 32K 2V 28-QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.MA180023.pdf
(528 pages)
2.PIC18LF24J10-ISS.pdf
(32 pages)
3.PIC18F24J11-ISS.pdf
(14 pages)
Specifications of PIC18F25J11-I/ML
Core Size
8-Bit
Program Memory Size
32KB (16K x 16)
Core Processor
PIC
Speed
48MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
FLASH
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2.15 V ~ 3.6 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Controller Family/series
PIC18
No. Of I/o's
16
Ram Memory Size
3.6875KB
Cpu Speed
48MHz
No. Of Timers
5
Interface
EUSART, I2C, SPI
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3776 B
Interface Type
EUSART, I2C, SPI
Maximum Clock Frequency
48 MHz
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM183022, DM183032, DV164136, MA180023
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 10 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F25J11-I/ML
Manufacturer:
MICROCHIP
Quantity:
4 000
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PIC18F46J11 FAMILY
18.5.5
The addressing procedure for the I
the first byte after the Start condition usually
determines which device will be the slave addressed by
the master. The exception is the general call address
which can address all devices. When this address is
used, all devices should, in theory, respond with an
Acknowledge.
The general call address is one of eight addresses
reserved for specific purposes by the I
consists of all ‘0’s with R/W = 0.
The general call address is recognized when the
General
(SSPxCON2<7> set). Following a Start bit detect, 8 bits
are shifted into the SSPxSR and the address is
compared against the SSPxADD. It is also compared to
the general call address and fixed in hardware.
FIGURE 18-17:
18.5.6
Master mode is enabled by setting and clearing the
appropriate SSPM bits in SSPxCON1 and by setting
the SSPEN bit. In Master mode, the SCLx and SDAx
lines are manipulated by the MSSP hardware if the
TRIS bits are set.
Master mode of operation is supported by interrupt
generation on the detection of the Start and Stop con-
ditions. The Start (S) and Stop (P) bits are cleared from
a Reset or when the MSSP module is disabled. Control
of the I
the bus is Idle, with both the Start and Stop bits clear.
In Firmware Controlled Master mode, user code
conducts all I
Stop bit conditions.
DS39932C-page 304
GCEN (SSPxCON2<7>)
SSPOV (SSPxCON1<6>)
SDAx
SCLx
SSPxIF
BF (SSPxSTAT<0>)
2
C bus may be taken when the Stop bit is set, or
Call
GENERAL CALL ADDRESS
SUPPORT
MASTER MODE
2
C bus operations based on Start and
Enable
S
SLAVE MODE GENERAL CALL ADDRESS SEQUENCE
(7-BIT OR 10-BIT ADDRESSING MODE)
bit,
1
2
GCEN,
General Call Address
2
C bus is such that
3
2
4
C protocol. It
is
5
enabled
6
7
R/W = 0
8
ACK
If the general call address matches, the SSPxSR is
transferred to the SSPxBUF, the BF flag bit is set (eighth
bit), and on the falling edge of the ninth bit (ACK bit), the
SSPxIF interrupt flag bit is set.
When the interrupt is serviced, the source for the
interrupt can be checked by reading the contents of the
SSPxBUF. The value can be used to determine if the
address was device-specific or a general call address.
In 10-bit mode, the SSPxADD is required to be updated
for the second half of the address to match and the UA
bit is set (SSPxSTAT<1>). If the general call address is
sampled when the GCEN bit is set, while the slave is
configured in 10-Bit Addressing mode, then the second
half of the address is not necessary, the UA bit will not
be set and the slave will begin receiving data after the
Acknowledge (Figure 18-17).
Once Master mode is enabled, the user has six
options.
1.
2.
3.
4.
5.
6.
Address is compared to General Call Address
after ACK, set interrupt
9
Assert a Start condition on SDAx and SCLx.
Assert a Repeated Start condition on SDAx and
SCLx.
Write to the SSPxBUF register initiating
transmission of data/address.
Configure the I
Generate an Acknowledge condition at the end
of a received byte of data.
Generate a Stop condition on SDAx and SCLx.
D7
1
D6
2
Cleared in software
SSPxBUF is read
Receiving Data
D5
3
D4
2
4
C port to receive data.
© 2009 Microchip Technology Inc.
D3
5
D2
6
D1
7
D0
8
ACK
9
‘0’
‘1’
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