PIC18F25J11-I/ML Microchip Technology, PIC18F25J11-I/ML Datasheet - Page 285
![IC PIC MCU FLASH 32K 2V 28-QFN](/photos/6/81/68120/150-28-qfn_sml.jpg)
PIC18F25J11-I/ML
Manufacturer Part Number
PIC18F25J11-I/ML
Description
IC PIC MCU FLASH 32K 2V 28-QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.MA180023.pdf
(528 pages)
2.PIC18LF24J10-ISS.pdf
(32 pages)
3.PIC18F24J11-ISS.pdf
(14 pages)
Specifications of PIC18F25J11-I/ML
Core Size
8-Bit
Program Memory Size
32KB (16K x 16)
Core Processor
PIC
Speed
48MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
FLASH
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2.15 V ~ 3.6 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Controller Family/series
PIC18
No. Of I/o's
16
Ram Memory Size
3.6875KB
Cpu Speed
48MHz
No. Of Timers
5
Interface
EUSART, I2C, SPI
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3776 B
Interface Type
EUSART, I2C, SPI
Maximum Clock Frequency
48 MHz
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM183022, DM183032, DV164136, MA180023
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 10 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F25J11-I/ML
Manufacturer:
MICROCHIP
Quantity:
4 000
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18.5
The MSSP module in I
master and slave functions (including general call
support), and provides interrupts on Start and Stop bits
in hardware to determine a free bus (multi-master
function). The MSSP module implements the standard
mode specifications and 7-bit and 10-bit addressing.
Two pins are used for data transfer:
• Serial Clock (SCLx) –
• Serial Data (SDAx) –
The user must configure these pins as inputs by setting
the associated TRIS bits.
FIGURE 18-7:
© 2009 Microchip Technology Inc.
Note:
SDAx
SCLx
RB4/PMA1/KBI0/SCK1/SCL1/RP7 or
RD0/PMD0/SCL2
RB5/PMA0/KBI1/SDI1/SDA1/RP8 or
RD1/PMD1/SDA2
Only port I/O names are used in this diagram for
the sake of brevity. Refer to the text for a full list of
multiplexed functions.
I
2
C Mode
Read
Shift
Clock
MSb
SSPxADD reg
Address Mask
Stop bit Detect
Match Detect
SSPxBUF reg
SSPxSR reg
MSSPx BLOCK DIAGRAM
(I
Start and
2
2
C mode fully implements all
C™ MODE)
LSb
Write
Addr Match
Set, Reset
S, P bits
(SSPxSTAT reg)
Internal
Data Bus
PIC18F46J11 FAMILY
18.5.1
The MSSP module has six registers for I
These are:
• MSSPx Control Register 1 (SSPxCON1)
• MSSPx Control Register 2 (SSPxCON2)
• MSSPx Status Register (SSPxSTAT)
• Serial Receive/Transmit Buffer Register
• MSSPx Shift Register (SSPxSR) – Not directly
• MSSPx Address Register (SSPxADD)
• MSSPx 7-Bit Address Mask Register (SSPxMSK)
SSPxCON1, SSPxCON2 and SSPxSTAT are the
control and status registers in I
SSPxCON1 and SSPxCON2 registers are readable and
writable. The lower six bits of the SSPxSTAT are
read-only. The upper two bits of the SSPxSTAT are
read/write.
SSPxSR is the shift register used for shifting data in or
out. SSPxBUF is the buffer register to which data
bytes are written to or read from.
SSPxADD contains the slave device address when the
MSSP is configured in I
MSSP is configured in Master mode, the lower seven
bits of SSPxADD act as the Baud Rate Generator
(BRG) reload value.
SSPxMSK holds the slave address mask value when
the module is configured for 7-Bit Address Masking
mode. While it is a separate register, it shares the same
SFR address as SSPxADD; it is only accessible when
the SSPM<3:0> bits are specifically set to permit
access.
Section 18.5.3.4 “7-Bit Address Masking Mode”.
In receive operations, SSPxSR and SSPxBUF
together, create a double-buffered receiver. When
SSPxSR receives a complete byte, it is transferred to
SSPxBUF and the SSPxIF interrupt is set.
During
double-buffered. A write to SSPxBUF will write to both
SSPxBUF and SSPxSR.
(SSPxBUF)
accessible
transmission,
Additional
REGISTERS
details
2
the
C Slave mode. When the
2
C mode operation. The
SSPxBUF
are
DS39932C-page 285
provided
2
C operation.
is
not
in
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