PIC18F25J11-I/ML Microchip Technology, PIC18F25J11-I/ML Datasheet - Page 282
![IC PIC MCU FLASH 32K 2V 28-QFN](/photos/6/81/68120/150-28-qfn_sml.jpg)
PIC18F25J11-I/ML
Manufacturer Part Number
PIC18F25J11-I/ML
Description
IC PIC MCU FLASH 32K 2V 28-QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.MA180023.pdf
(528 pages)
2.PIC18LF24J10-ISS.pdf
(32 pages)
3.PIC18F24J11-ISS.pdf
(14 pages)
Specifications of PIC18F25J11-I/ML
Core Size
8-Bit
Program Memory Size
32KB (16K x 16)
Core Processor
PIC
Speed
48MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
FLASH
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2.15 V ~ 3.6 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Controller Family/series
PIC18
No. Of I/o's
16
Ram Memory Size
3.6875KB
Cpu Speed
48MHz
No. Of Timers
5
Interface
EUSART, I2C, SPI
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3776 B
Interface Type
EUSART, I2C, SPI
Maximum Clock Frequency
48 MHz
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM183022, DM183032, DV164136, MA180023
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 10 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F25J11-I/ML
Manufacturer:
MICROCHIP
Quantity:
4 000
- Current page: 282 of 528
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PIC18F46J11 FAMILY
18.4.6
The following steps would typically be taken to enable
and use the SPI DMA module:
1.
2.
3.
DS39932C-page 282
Configure the I/O pins, which will be used by
MSSP2.
a)
b)
c)
d)
Configure and enable MSSP2 for the desired
SPI operating mode.
a)
b)
Configure the SPI DMA engine.
a)
b)
c)
d)
e)
Assign SCK2, SDO2, SDI2 and SS2 to RPn
pins as appropriate for the SPI mode which
will be used. Only functions which will be
used need to be assigned to a pin.
Initialize the associated LATx registers for
the desired Idle SPI bus state.
If Open-Drain Output mode on SDO2 and
SCK2 (Master mode) is desired, set
ODCON3<1>.
Configure corresponding TRISx bits for
each I/O pin used
Select the desired operating mode (Master
or Slave, SPI Mode 0, 1, 2 and 3) and
configure the module by writing to the
SSP2STAT and SSP2CON1 registers.
Enable MSSP2 by setting SSP2CON1<5> = 1.
Select the desired operating mode by
writing
DMACON2 and DMACON1.
Initialize the TXADDRH/TXADDRL Pointer
(Full-Duplex or Half-Duplex Transmit Only
mode).
Initialize the RXADDRH/RXADDRL Pointer
(Full-Duplex or Half-Duplex Receive Only
mode).
Initialize the DMABCH/DMABCL Byte Count
register with the number of bytes to be
transferred in the next SPI DMA operation.
Set the DMAEN bit (DMACON1<0>).
In SPI Master modes, this will initiate a DMA
transaction. In SPI Slave modes, this will
complete the initialization process, and the
module will now be ready to begin receiving
and/or transmitting data to the master
device
transaction.
USING THE SPI DMA MODULE
once
the
appropriate
the
master
values
starts
the
to
4.
Example 18-2 provides example code demonstrating
the initialization process and the steps needed to use
the SPI DMA module to perform a 512-byte
Full-Duplex, Master mode transfer.
Detect the SSP2IF interrupt condition (PIR3<7).
a)
b)
If the interrupt was configured to occur at
the completion of the SPI DMA transaction,
the DMAEN bit (DMACON1<0>) will be
clear. User firmware may prepare the
module for another transaction by repeating
steps 3.b through 3.e.
If the interrupt was configured to occur prior
to the completion of the SPI DMA trans-
action, the DMAEN bit may still be set,
indicating the transaction is still in progress.
User firmware would typically use this inter-
rupt condition to begin preparing new data
for the next DMA transaction. Firmware
should not repeat steps 3.b. through 3.e.
until the DMAEN bit is cleared by the
hardware, indicating the transaction is
complete.
© 2009 Microchip Technology Inc.
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