DSPIC30F2012-30I/SP Microchip Technology, DSPIC30F2012-30I/SP Datasheet - Page 127

IC DSPIC MCU/DSP 12K 28DIP

DSPIC30F2012-30I/SP

Manufacturer Part Number
DSPIC30F2012-30I/SP
Description
IC DSPIC MCU/DSP 12K 28DIP
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr

Specifications of DSPIC30F2012-30I/SP

Program Memory Type
FLASH
Program Memory Size
12KB (4K x 24)
Package / Case
28-DIP (0.300", 7.62mm)
Core Processor
dsPIC
Core Size
16-Bit
Speed
30 MIPs
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
20
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 10x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC30F
Core
dsPIC
Maximum Clock Frequency
30 MHz
Number Of Programmable I/os
12
Data Ram Size
1 KB
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM300027, DM330011, DM300018, DM183021
Minimum Operating Temperature
- 40 C
Core Frequency
30MHz
Embedded Interface Type
I2C, SPI, UART
No. Of I/o's
20
Flash Memory Size
12KB
Supply Voltage Range
2.5V To 5.5V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
DSPIC30F201230ISP

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DSPIC30F2012-30I/SP
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
17.3
The PIC18F1220/1320 differentiates between various
kinds of Reset:
a)
b)
c)
d)
e)
f)
g)
h)
FIGURE 17-2:
17.3.1
A power-on event will generate an internal POR pulse
when a V
at the POR circuit threshold voltage (V
nominally 1.85V. The device supply voltage character-
istics must meet specified starting voltage and rise rate
requirements. The POR pulse will reset a POR timer
and place the device in the Reset state. The POR also
selects the device clock source identified by the
oscillator configuration fuses.
© 2006 Microchip Technology Inc.
Power-on Reset (POR)
MCLR Reset during normal operation
MCLR Reset during Sleep
Watchdog Timer (WDT) Reset (during normal
operation)
Programmable Brown-out Reset (BOR)
RESET Instruction
Reset caused by trap lockup (TRAPR)
Reset caused by illegal opcode or by using an
uninitialized W register as an address pointer
(IOPUWR)
MCLR
V
DD
Reset
DD
Instruction
POR: POWER-ON RESET
RESET
rise is detected. The Reset pulse will occur
Trap Conflict
Illegal Opcode/
Uninitialized W Register
Brown-out
V
Sleep or Idle
Module
DD
Detect
WDT
Reset
RESET SYSTEM BLOCK DIAGRAM
Rise
BOREN
Glitch Filter
Digital
POR
dsPIC30F2011/2012/3012/3013
POR
) which is
BOR
Different registers are affected in different ways by var-
ious Reset conditions. Most registers are not affected
by a WDT wake-up since this is viewed as the resump-
tion of normal operation. Status bits from the RCON
register are set or cleared differently in different Reset
situations, as indicated in Table 17-5. These bits are
used in software to determine the nature of the Reset.
A block diagram of the On-Chip Reset Circuit is shown
in Figure 17-2.
A MCLR noise filter is provided in the MCLR Reset
path. The filter detects and ignores small pulses.
Internally generated Resets do not drive MCLR pin low.
The POR circuit inserts a small delay, T
nominally 10 s and ensures that the device bias cir-
cuits are stable. Furthermore, a user selected power-
up time-out (T
is based on device Configuration bits and can be 0 ms
(no delay), 4 ms, 16 ms or 64 ms. The total delay is at
device power-up, T
have expired, SYSRST will be negated on the next
leading edge of the Q1 clock and the PC will jump to the
Reset vector.
The timing for the SYSRST signal is shown in
Figure 17-3 through Figure 17-5.
PWRT
) is applied. The T
POR
S
R
+ T
PWRT
Q
. When these delays
DS70139E-page 125
PWRT
POR
SYSRST
parameter
, which is

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