DSPIC30F2012-30I/SP Microchip Technology, DSPIC30F2012-30I/SP Datasheet - Page 35

• Manufacturer Part Number: DSPIC30F2012-30I/SP
• Description: IC DSPIC MCU/DSP 12K 28DIP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F2012-30I/SP

• Program Memory Type: FLASH
• Program Memory Size: 12KB (4K x 24)
• Package / Case: 28-DIP (0.300", 7.62mm)
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 20
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 10x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC30F
• Core: dsPIC
• Maximum Clock Frequency: 30 MHz
• Number Of Programmable I/os: 12
• Data Ram Size: 1 KB
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM300027, DM330011, DM300018, DM183021
• Minimum Operating Temperature: - 40 C
• Core Frequency: 30MHz
• Embedded Interface Type: I2C, SPI, UART
• No. Of I/o's: 20
• Flash Memory Size: 12KB
• Supply Voltage Range: 2.5V To 5.5V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: DSPIC30F201230ISP

3.2
The core has two data spaces. The data spaces can be
considered either separate (for some DSP instruc-
tions), or as one unified linear address range (for MCU
instructions). The data spaces are accessed using two
Address Generation Units (AGUs) and separate data
paths.
3.2.1
The data space memory is split into two blocks, X and
Y data space. A key element of this architecture is that
Y space is a subset of X space, and is fully contained
within X space. In order to provide an apparent Linear
Addressing space, X and Y spaces have contiguous
addresses.
FIGURE 3-7:
© 2006 Microchip Technology Inc.
Data Address Space
DATA SPACE MEMORY MAP
2 Kbyte
SFR Space
Optionally
Mapped
into Program
Memory
SRAM Space
1 Kbyte
dsPIC30F2011/2012 DATA SPACE MEMORY MAP
Address
MSB
0x1FFF
0x0001
0x07FF
0x0801
0x09FF
0x0A01
0x0BFF
0x0C01
0x8001
0xFFFF
dsPIC30F2011/2012/3012/3013
MSB
Unimplemented (X)
Y Data RAM (Y)
X Data RAM (X)
16 bits
SFR Space
X Data
When executing any instruction other than one of the
MAC class of instructions, the X block consists of the 64-
Kbyte data address space (including all Y addresses).
When executing one of the MAC class of instructions,
the X block consists of the 64-Kbyte data address
space, excluding the Y address block (for data reads
only). In other words, all other instructions regard the
entire data memory as one composite address space.
The MAC class instructions extract the Y address space
from data space and address it using EAs sourced from
W10 and W11. The remaining X data space is
addressed using W8 and W9. Both address spaces are
concurrently accessed only with the MAC class
instructions.
The data space memory map for the dsPIC30F2011
and dsPIC30F2012 is shown in Figure 3-7. The data
space memory map for the dsPIC30F3012 and
dsPIC30F3013 is shown in Figure 3-8.
LSB
0x0000
0x07FE
0x0800
0x09FE
0x0A00
0x0BFE
0x0C00
0x1FFE
0x8000
0xFFFE
Address
LSB
8 Kbyte
Near
Data
Space
DS70139E-page 33