DSPIC30F2012-30I/SP Microchip Technology, DSPIC30F2012-30I/SP Datasheet - Page 92

• Manufacturer Part Number: DSPIC30F2012-30I/SP
• Description: IC DSPIC MCU/DSP 12K 28DIP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F2012-30I/SP

• Program Memory Type: FLASH
• Program Memory Size: 12KB (4K x 24)
• Package / Case: 28-DIP (0.300", 7.62mm)
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 20
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 10x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC30F
• Core: dsPIC
• Maximum Clock Frequency: 30 MHz
• Number Of Programmable I/os: 12
• Data Ram Size: 1 KB
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM300027, DM330011, DM300018, DM183021
• Minimum Operating Temperature: - 40 C
• Core Frequency: 30MHz
• Embedded Interface Type: I2C, SPI, UART
• No. Of I/o's: 20
• Flash Memory Size: 12KB
• Supply Voltage Range: 2.5V To 5.5V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: DSPIC30F201230ISP

dsPIC30F2011/2012/3012/3013
Figure 13-2 depicts the a master/slave connection
between two processors. In Master mode, the clock is
generated by prescaling the system clock. Data is
transmitted as soon as a value is written to SPI1BUF.
The interrupt is generated at the middle of the transfer
of the last bit.
In Slave mode, data is transmitted and received as
external clock pulses appear on SCK. Again, the inter-
rupt is generated when the last bit is latched. If SS1
control is enabled, then transmission and reception are
enabled only when SS1 = low. The SDO1 output will be
disabled in SS1 mode with SS1 high.
The clock provided to the module is (F
clock is then prescaled by the primary (PPRE<1:0>)
and the secondary (SPRE<2:0>) prescale factors. The
CKE bit determines whether transmit occurs on transi-
tion from active clock state to Idle clock state, or vice
versa. The CKP bit selects the Idle state (high or low)
for the clock.
13.1.1
A control bit, MODE16 (SPI1CON<10>), allows the
module to communicate in either 16-bit or 8-bit mode.
16-bit operation is identical to 8-bit operation except
that the number of bits transmitted is 16 instead of 8.
FIGURE 13-2:
DS70139E-page 90
WORD AND BYTE
COMMUNICATION
MSb
PROCESSOR 1
Serial Input Buffer
SPI MASTER/SLAVE CONNECTION
SPI Master
Shift Register
(SPI1BUF)
(SPI1SR)
LSb
OSC
SDO1
SCK1
SDI1
/4). This
Serial Clock
The user software must disable the module prior to
changing the MODE16 bit. The SPI module is reset
when the MODE16 bit is changed by the user.
A basic difference between 8-bit and 16-bit operation is
that the data is transmitted out of bit 7 of the SPI1SR
for 8-bit operation, and data is transmitted out of bit 15
of the SPI1SR for 16-bit operation. In both modes, data
is shifted into bit 0 of the SPI1SR.
13.1.2
A control bit, DISSDO, is provided to the SPI1CON reg-
ister to allow the SDO1 output to be disabled. This will
allow the SPI module to be connected in an input only
configuration. SDO1 can also be used for general
purpose I/O.
13.2
The module supports a basic framed SPI protocol in
Master or Slave mode. The control bit, FRMEN,
enables framed SPI support and causes the SS1 pin to
perform the Frame Synchronization Pulse (FSYNC)
function. The control bit, SPIFSD, determines whether
the SS1 pin is an input or an output (i.e., whether the
module receives or generates the Frame Synchroniza-
tion Pulse). The frame pulse is an active-high pulse for
a single SPI clock cycle. When Frame Synchronization
is enabled, the data transmission starts only on the
subsequent transmit edge of the SPI clock.
SDO1
SCK1
SDI1
Framed SPI Support
SDO1 DISABLE
MSb
Serial Input Buffer
Shift Register
PROCESSOR 2
(SPI1BUF)
(SPI1SR)
SPI Slave
© 2006 Microchip Technology Inc.
LSb