PIC18F27J53-I/SP Microchip Technology, PIC18F27J53-I/SP Datasheet - Page 232

• Manufacturer Part Number: PIC18F27J53-I/SP
• Description: IC PIC MCU 128KB FLASH 28SPDIP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F27J53-I/SP

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: *
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 10x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3.8 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 8
• Operating Supply Voltage: 2.15 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: - 40 C
• Controller Family/series: PIC18
• Cpu Speed: 48MHz
• Embedded Interface Type: I2C, SPI, USART
• Digital Ic Case Style: DIP
• Supply Voltage Range: 1.8V To 5.5V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18(L)F2X/4XK22
15.5.4 SLAVE MODE 10-BIT ADDRESS
This section describes a standard sequence of events
for the MSSPx module configured as an I
10-bit Addressing mode.
Figure 15-19
description.
This is a step by step process of what must be done by
slave software to accomplish I
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. Slave clears SSPxIF.
11. Slave reads the received matching address
12. Slave loads high address into SSPxADD.
13. Master clocks a data byte to the slave and clocks
14. If SEN bit of SSPxCON2 is set, CKP is cleared
15. Slave clears SSPxIF.
16. Slave reads the received byte from SSPxBUF
17. If SEN is set the slave sets CKP to release the
18. Steps 13-17 repeat for each received byte.
19. Master sends Stop to end the transmission.
DS41412D-page 232
Note: Updates to the SSPxADD register are not
Note: If the low address does not match, SSPxIF
Bus starts Idle.
Master sends Start condition; S bit of SSPx-
STAT is set; SSPxIF is set if interrupt on Start
detect is enabled.
Master sends matching high address with R/W
bit clear; UA bit of the SSPxSTAT register is set.
Slave sends ACK and SSPxIF is set.
Software clears the SSPxIF bit.
Software reads received address from SSPxBUF
clearing the BF flag.
Slave loads low address into SSPxADD,
releasing SCLx.
Master sends matching low address byte to the
slave; UA bit is set.
Slave sends ACK and SSPxIF is set.
from SSPxBUF clearing BF.
out the slaves ACK on the 9th SCLx pulse;
SSPxIF is set.
by hardware and the clock is stretched.
clearing BF.
SCLx.
RECEPTION
allowed until after the ACK sequence.
and UA are still set so that the slave soft-
ware can set SSPxADD back to the high
address. BF is not set because there is no
match. CKP is unaffected.
and is used as a visual reference for this
2
C communication.
2
C slave in
Preliminary
15.5.5 10-BIT ADDRESSING WITH ADDRESS
Reception using 10-bit addressing with AHEN or
DHEN set is the same as with 7-bit modes. The only
difference is the need to update the SSPxADD register
using the UA bit. All functionality, specifically when the
CKP bit is cleared and SCLx line is held low are the
same.
slave in 10-bit addressing with AHEN set.
Figure 15-21
transmitter in 10-bit Addressing mode.
Figure 15-20
OR DATA HOLD
shows a standard waveform for a slave
can be used as a reference of a
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