PIC18F27J53-I/SP Microchip Technology, PIC18F27J53-I/SP Datasheet - Page 45

• Manufacturer Part Number: PIC18F27J53-I/SP
• Description: IC PIC MCU 128KB FLASH 28SPDIP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F27J53-I/SP

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: *
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 10x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3.8 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 8
• Operating Supply Voltage: 2.15 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: - 40 C
• Controller Family/series: PIC18
• Cpu Speed: 48MHz
• Embedded Interface Type: I2C, SPI, USART
• Digital Ic Case Style: DIP
• Supply Voltage Range: 1.8V To 5.5V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

FIGURE 2-11:
TABLE 2-4:
TABLE 2-5:
 2010 Microchip Technology Inc.
INTCON
IPR2
OSCCON
OSCCON2
OSCTUNE
PIE2
PIR2
Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used by Clock Sources.
CONFIG1H
CONFIG2L
CONFIG3H
Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for Clock Sources.
Clock Monitor Output
Name
Name
Sample Clock
Note:
OSCFIF
GIE/GIEH PEIE/GIEL
System
PLLRDY SOSCRUN
Output
OSCFIP
INTSRC
OSCFIE
OSCFIF
IDLEN
Clock
Bit 7
MCLRE
(Q)
REGISTERS ASSOCIATED WITH CLOCK SOURCES
CONFIGURATION REGISTERS ASSOCIATED WITH CLOCK SOURCES
IESO
The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in
this example have been chosen for clarity.
Bit 7
—
FSCM TIMING DIAGRAM
PLLEN
FCMEN PRICLKEN PLLCFG
C1IP
C1IE
Bit 6
C1IF
Bit 6
—
—
IRCF<2:0>
P2BMX
TMR0IE
Test
Bit 5
C2IP
C2IE
Bit 5
C2IF
—
—
Preliminary
T3CMX
MFIOSEL SOSCGO
Bit 4
INT0IE
EEIP
EEIE
EEIF
Bit 4
BORV<1:0>
HFOFST CCP3MX PBADEN CCP2MX
Bit 3
BCL1IP
BCL1IE
BCL1IF
OSTS
PIC18(L)F2X/4XK22
RBIE
Bit 3
TUN<5:0>
Test
Oscillator
Failure
Bit 2
BOREN<1:0>
TMR0IF
HFIOFS
HLVDIP
HLVDIE
HLVDIF
PRISD
FOSC<3:0>
Bit 2
Bit 1
MFIOFS LFIOFS
TMR3IP CCP2IP
TMR3IE CCP2IE
TMR3IF CCP2IF
INT0IF
Bit 1
Detected
SCS<1:0>
Failure
PWRTEN
Bit 0
Test
RBIF
Bit 0
DS41412D-page 45
Register
Register
on Page
on Page
351
352
354
115
128
124
119
32
33
37