PIC18F27J53-I/SP Microchip Technology, PIC18F27J53-I/SP Datasheet - Page 41

• Manufacturer Part Number: PIC18F27J53-I/SP
• Description: IC PIC MCU 128KB FLASH 28SPDIP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F27J53-I/SP

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: *
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 10x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3.8 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 8
• Operating Supply Voltage: 2.15 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: - 40 C
• Controller Family/series: PIC18
• Cpu Speed: 48MHz
• Embedded Interface Type: I2C, SPI, USART
• Digital Ic Case Style: DIP
• Supply Voltage Range: 1.8V To 5.5V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

TABLE 2-3:
2.9
The system clock source can be switched between
external and internal clock sources via software using
the System Clock Select (SCS<1:0>) bits of the
OSCCON register.
PIC18(L)F2X/4XK22 devices contain circuitry to pre-
vent clock “glitches” when switching between clock
sources. A short pause in the device clock occurs dur-
ing the clock switch. The length of this pause is the sum
of two cycles of the old clock source and three to four
cycles of the new clock source. This formula assumes
that the new clock source is stable.
Clock transitions are discussed in greater detail in
Section 3.1.2 “Entering Power-Managed Modes”.
2.9.1
The System Clock Select (SCS<1:0>) bits of the
OSCCON register select the system clock source that
is used for the CPU and peripherals.
• When SCS<1:0> = 00, the system clock source is
• When SCS<1:0> = 10, the system clock source is
• When SCS<1:0> = 01, the system clock source is
 2010 Microchip Technology Inc.
RC, INTOSC with CLKOUT Floating, external resistor should pull high
RC with IO
INTOSC with IO
EC with IO
EC with CLKOUT
LP, XT, HS
Note:
determined by configuration of the FOSC<3:0>
bits in the CONFIG1H Configuration register.
chosen by the internal oscillator frequency
selected by the INTSRC bit of the OSCTUNE
register, the MFIOSEL bit of the OSCCON2
register and the IRCF<2:0> bits of the OSCCON
register.
the 32.768 kHz secondary oscillator shared with
Timer1, Timer3 and Timer5.
OSC Mode
Clock Switching
See
SYSTEM CLOCK SELECT
(SCS<1:0>) BITS
Table 4-2
OSC1 AND OSC2 PIN STATES IN SLEEP MODE
in Section 4.0 “Reset” for time-outs due to Sleep and MCLR Reset.
Floating, external resistor should pull high
Configured as PORTA, bit 7
Floating, pulled by external clock
Feedback inverter disabled at quiescent
voltage level
Floating, pulled by external clock
OSC1 Pin
Preliminary
After a Reset, the SCS<1:0> bits of the OSCCON
register are always cleared.
2.9.2
The Oscillator Start-up Time-out Status (OSTS) bit of
the OSCCON register indicates whether the system
clock is running from the external clock source, as
defined by the FOSC<3:0> bits in the CONFIG1H
Configuration register, or from the internal clock
source. In particular, when the primary oscillator is the
source of the primary clock, OSTS indicates that the
Oscillator Start-up Timer (OST) has timed out for LP,
XT or HS modes.
Note:
PIC18(L)F2X/4XK22
Any automatic clock switch, which may
occur from Two-Speed Start-up or Fail-
Safe Clock Monitor, does not update the
SCS<1:0> bits of the OSCCON register.
The user can monitor the SOSCRUN,
MFIOFS
OSCCON2 register, and the HFIOFS and
OSTS bits of the OSCCON register to
determine the current system clock source.
OSCILLATOR START-UP TIME-OUT
STATUS (OSTS) BIT
At logic low (clock/4 output)
Configured as PORTA, bit 6
Configured as PORTA, bit 6
Configured as PORTA, bit 6
At logic low (clock/4 output)
Feedback inverter disabled at quiescent
voltage level
and
OSC2 Pin
LFIOFS
DS41412D-page 41
bits
of
the