PIC18F27J53-I/SP Microchip Technology, PIC18F27J53-I/SP Datasheet - Page 67

• Manufacturer Part Number: PIC18F27J53-I/SP
• Description: IC PIC MCU 128KB FLASH 28SPDIP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F27J53-I/SP

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: *
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 10x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3.8 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 8
• Operating Supply Voltage: 2.15 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: - 40 C
• Controller Family/series: PIC18
• Cpu Speed: 48MHz
• Embedded Interface Type: I2C, SPI, USART
• Digital Ic Case Style: DIP
• Supply Voltage Range: 1.8V To 5.5V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.6
Some registers are unaffected by a Reset. Their status
is unknown on POR and unchanged by all other
Resets. All other registers are forced to a “Reset state”
depending on the type of Reset that occurred.
Most registers are not affected by a WDT wake-up,
since this is viewed as the resumption of normal
operation. Status bits from the RCON register, RI, TO,
PD, POR and BOR, are set or cleared differently in
different Reset situations, as indicated in
These bits are used by software to determine the
nature of the Reset.
TABLE 4-3:
TABLE 4-4:
 2010 Microchip Technology Inc.
Power-on Reset
RESET Instruction
Brown-out Reset
MCLR during Power-Managed
Run Modes
MCLR during Power-Managed
Idle Modes and Sleep Mode
WDT Time-out during Full Power
or Power-Managed Run Mode
MCLR during Full Power
Execution
Stack Full Reset (STVREN = 1)
Stack Underflow Reset
(STVREN = 1)
Stack Underflow Error (not an
actual Reset, STVREN = 0)
WDT Time-out during Power-
Managed Idle or Sleep Modes
Interrupt Exit from Power-
Managed Modes
Legend: u = unchanged
Note 1:
RCON
STKPTR
Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for Resets.
Name
2:
Reset State of Registers
When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the
interrupt vector (008h or 0018h).
Reset state is ‘1’ for SBOREN and unchanged for all other Resets when software BOR is enabled
(BOREN<1:0> Configuration bits = 01). Otherwise, the Reset state is ‘0’.
Condition
STKFUL
IPEN
Bit 7
STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION
FOR RCON REGISTER
REGISTERS ASSOCIATED WITH RESETS
SBOREN
STKUNF
Bit 6
Program
PC + 2
Counter
PC + 2
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
Bit 5
—
—
(1)
Table
SBOREN
4-3.
Preliminary
u
u
u
u
u
u
u
u
u
u
u
Bit 4
1
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
RI
RCON Register
Table 5-2
Special Function Registers. The table identifies
differences between Power-On Reset (POR)/Brown-
Out Reset (BOR) and all other Resets, (i.e., Master
Clear, WDT
Additionally, the table identifies register bits that are
changed when the device receives a wake-up from
WDT or other interrupts.
RI
1
0
1
u
u
u
u
u
u
u
u
u
Bit 3
TO
PIC18(L)F2X/4XK22
TO
1
u
1
1
1
0
u
u
u
u
0
u
STKPTR<4:0>
describes the Reset states for all of the
Bit 2
PD
PD
1
u
1
u
0
u
u
u
u
u
0
0
Resets,
POR BOR STKFUL
0
u
u
u
u
u
u
u
u
u
u
u
Bit 1
POR
STKFUL, STKUNF, etc.).
0
u
0
u
u
u
u
u
u
u
u
u
STKPTR Register
Bit 0
BOR
0
u
u
u
u
u
u
1
u
u
u
u
DS41412D-page 67
STKUNF
Register
on Page
60
72
0
u
u
u
u
u
u
u
1
1
u
u