PIC18F27J53-I/SP Microchip Technology, PIC18F27J53-I/SP Datasheet - Page 236

• Manufacturer Part Number: PIC18F27J53-I/SP
• Description: IC PIC MCU 128KB FLASH 28SPDIP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F27J53-I/SP

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: *
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 10x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3.8 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 8
• Operating Supply Voltage: 2.15 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: - 40 C
• Controller Family/series: PIC18
• Cpu Speed: 48MHz
• Embedded Interface Type: I2C, SPI, USART
• Digital Ic Case Style: DIP
• Supply Voltage Range: 1.8V To 5.5V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18(L)F2X/4XK22
15.5.6 CLOCK STRETCHING
Clock stretching occurs when a device on the bus
holds the SCLx line low effectively pausing communi-
cation. The slave may stretch the clock to allow more
time to handle data or prepare a response for the mas-
ter device. A master device is not concerned with
stretching as anytime it is active on the bus and not
transferring data it is stretching. Any stretching done
by a slave is invisible to the master software and han-
dled by the hardware that generates SCLx.
The CKP bit of the SSPxCON1 register is used to
control stretching in software. Any time the CKP bit is
cleared, the module will wait for the SCLx line to go
low and then hold it. Setting CKP will release SCLx
and allow more communication.
15.5.6.1 Normal Clock Stretching
Following an ACK if the R/W bit of SSPxSTAT is set, a
read request, the slave hardware will clear CKP. This
allows the slave time to update SSPxBUF with data to
transfer to the master. If the SEN bit of SSPxCON2 is
set, the slave hardware will always stretch the clock
after the ACK sequence. Once the slave is ready; CKP
is set by software and communication resumes.
FIGURE 15-23:
DS41412D-page 236
WR
SSPxCON1
SDAx
SCLx
CKP
Note 1: The BF bit has no effect on whether the
2: Previous versions of the module did not
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
clock will be stretched or not. This is
different than previous versions of the
module that would not stretch the clock,
clear CKP, if SSPxBUF was read before
the 9th falling edge of SCLx.
stretch the clock for a transmission if
SSPxBUF was loaded before the 9th fall-
ing edge of SCLx. It is now always cleared
for read requests.
CLOCK SYNCHRONIZATION TIMING
DX
Master device
asserts clock
Preliminary
15.5.6.2 10-bit Addressing Mode
In 10-bit Addressing mode, when the UA bit is set, the
clock is always stretched. This is the only time the
SCLx is stretched without CKP being cleared. SCLx is
released immediately after a write to SSPxADD.
15.5.6.3 Byte NACKing
When the AHEN bit of SSPxCON3 is set; CKP is
cleared by hardware after the 8th falling edge of SCLx
for a received matching address byte. When the
DHEN bit of SSPxCON3 is set; CKP is cleared after
the 8th falling edge of SCLx for received data.
Stretching after the 8th falling edge of SCLx allows the
slave to look at the received address or data and
decide if it wants to ACK the received data.
15.5.7 CLOCK SYNCHRONIZATION AND
Any time the CKP bit is cleared, the module will wait
for the SCLx line to go low and then hold it. However,
clearing the CKP bit will not assert the SCLx output
low until the SCLx output is already sampled low.
Therefore, the CKP bit will not assert the SCLx line
until an external I
asserted the SCLx line. The SCLx output will remain
low until the CKP bit is set and all other devices on the
I
to the CKP bit will not violate the minimum high time
requirement for SCLx (see
2
Master device
releases clock
C bus have released SCLx. This ensures that a write
Note: Previous versions of the module did not
THE CKP BIT
stretch the clock if the second address byte
did not match.
2
C master device has already
 2010 Microchip Technology Inc.
Figure
15-22).
DX ‚
–
1